LAN9311I-NZW Standard Microsystem (Smsc), LAN9311I-NZW Datasheet - Page 34

• Manufacturer Part Number: LAN9311I-NZW
• Manufacturer: Standard Microsystem (Smsc)

Specifications of LAN9311I-NZW

• Package: 128XVTQFP
• Phy/transceiver Interface: MII
• Number Of Primary Switch Ports: 2
• Maximum Data Rate: 100 Mbps
• Internal Memory Buffer Size: 32 KB
• Vlan Support: Yes
• Power Supply Type: Analog
• Minimum Single Supply Voltage: 3 V
• Maximum Single Supply Voltage: 3.6 V
• Maximum Supply Current: 0.295 A
• Maximum Power Dissipation: 1070 mW

Revision 1.7 (06-29-10)
77-79,
PIN
108
82
63
71
75
62
Note 3.7
System Reset
Management
Purpose I/O
Interrupt
General
NAME
Output
Power
Test 1
Test 2
Event
Input
Data
The input buffers are enabled when configured as GPIO inputs only.
GPIO[11:8]
SYMBOL
TEST1
TEST2
nRST
PME
IRQ
Table 3.7 Miscellaneous Pins
DATASHEET
BUFFER
IS/OD12/
O8/OD8
O8/OD8
Note 3.7
TYPE
(PU)
(PU)
O12
AI
AI
IS
34
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
General Purpose I/O Data: These general
purpose signals are fully programmable as either
push-pull outputs, open-drain outputs, or Schmitt-
triggered inputs by writing the
Configuration Register (GPIO_CFG)
Purpose I/O Data & Direction Register
(GPIO_DATA_DIR). For more information, refer to
Chapter 13, "GPIO/LED Controller," on page
Note:
Interrupt Output: Interrupt request output. The
polarity, source and buffer type of this signal is
programmable via the
Register
Chapter 5, "System Interrupts," on page
System Reset Input: This active low signal allows
external hardware to reset the LAN9311/LAN9311i.
The LAN9311/LAN9311i also contains an internal
power-on reset circuit. Thus, this signal may be left
unconnected if an external hardware reset is not
needed. When used, this signal must adhere to the
reset timing requirements as detailed in
15.5.2, "Reset and Configuration Strap Timing," on
page
Note:
Test 1: This pin must be tied to VDD33IO for
proper operation.
Test 2: This pin must be tied to VDD33IO for
proper operation.
Power Management Event: When programmed
accordingly, this signal is asserted upon detection
of a wakeup event. The polarity and buffer type of
this signal is programmable via the PME_EN bit of
the
(PMT_CTRL).
Refer to
Management," on page 36
information on the LAN9311/LAN9311i power
management features.
Power Management Control Register
445.
(IRQ_CFG). For more information, refer to
Chapter 4, "Clocking, Resets, and Power
The remaining GPIO[7:0] pins share
functionality with the LED output pins, as
described in
The LAN9311/LAN9311i must always be
read at least once after power-up or reset
to ensure that write operations function
properly.
DESCRIPTION
Table 3.1
Interrupt Configuration
for additional
SMSC LAN9311/LAN9311i
General Purpose I/O
and
Table
and
49.
Section
General
3.2.
Datasheet
163.