LAN9311I-NZW Standard Microsystem (Smsc), LAN9311I-NZW Datasheet - Page 389

• Manufacturer Part Number: LAN9311I-NZW
• Manufacturer: Standard Microsystem (Smsc)

Specifications of LAN9311I-NZW

• Package: 128XVTQFP
• Phy/transceiver Interface: MII
• Number Of Primary Switch Ports: 2
• Maximum Data Rate: 100 Mbps
• Internal Memory Buffer Size: 32 KB
• Vlan Support: Yes
• Power Supply Type: Analog
• Minimum Single Supply Voltage: 3 V
• Maximum Single Supply Voltage: 3.6 V
• Maximum Supply Current: 0.295 A
• Maximum Power Dissipation: 1070 mW

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
14.5.3.20
31:16
15:14
13:12
11:10
BITS
9:8
7:6
5:4
3:2
1:0
RESERVED
Priority 7 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 7.
Priority 6 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 6.
Priority 5 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 5.
Priority 4 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 4.
Priority 3 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 3.
Priority 2 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 2.
Priority 1 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 1.
Priority 0 traffic Class
These bits specify the egress queue that is used for packets with a priority
of 0.
Switch Engine Priority to Queue Register (SWE_PRI_TO_QUE)
This register specifies the Traffic Class table that maps the packet priority into the egress queues.
Register #:
1845h
DESCRIPTION
DATASHEET
389
Size:
32 bits
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
Revision 1.7 (06-29-10)
DEFAULT
11b
11b
10b
10b
01b
00b
00b
01b
-