MT48H4M32LFB5-75 IT:K Micron Technology Inc, MT48H4M32LFB5-75 IT:K Datasheet - Page 26
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MT48H4M32LFB5-75 IT:K
Manufacturer Part Number
MT48H4M32LFB5-75 IT:K
Description
DRAM Chip Mobile SDRAM 128M-Bit 4Mx32 1.8V 90-Pin VFBGA Tray
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr
Datasheet
1.MT48H8M16LFB4-6K.pdf
(86 pages)
Specifications of MT48H4M32LFB5-75 IT:K
Package
90VFBGA
Density
128 Mb
Address Bus Width
14 Bit
Operating Supply Voltage
1.8 V
Maximum Clock Rate
133 MHz
Maximum Random Access Time
8|5.4 ns
Operating Temperature
-40 to 85 °C
Functional Description
PDF: 09005aef832ff1ea
128mb_mobile_sdram_y35M.pdf - Rev. G 10/09 EN
Mobile LPSDR devices are quad-bank DRAM that operate at 1.8V and include a synchro-
nous interface. All signals are registered on the positive edge of the clock signal, CLK.
Read and write accesses to the device are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed se-
quence. Accesses begin with the registration of an ACTIVE command, followed by a
READ or WRITE command. The address bits registered coincident with the ACTIVE com-
mand are used to select the bank and row to be accessed (BA0 and BA1 select the bank).
The address bits registered coincident with the READ or WRITE command are used to
select the starting column location for the burst access.
The device provides for programmable READ or WRITE burst lengths. An auto pre-
charge function may be enabled to provide a self-timed row precharge that is initiated
at the end of the burst sequence.
The device uses an internal pipelined architecture that enables changing the column
address on every clock cycle to achieve high-speed, fully random access. Precharging
one bank while accessing one of the other three banks will hide the precharge cycles.
The device is designed to operate in 1.8V memory systems. An auto refresh mode is pro-
vided, along with power-saving, power-down, and deep power-down modes. All inputs
and outputs are LVTTL-compatible.
The device offers substantial advances in DRAM operating performance, including the
ability to synchronously burst data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks in order to hide precharge
time, and the capability to randomly change column addresses on each clock cycle dur-
ing a burst access.
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
Functional Description
©2008 Micron Technology, Inc. All rights reserved.