MT48H4M32LFB5-75 IT:K Micron Technology Inc, MT48H4M32LFB5-75 IT:K Datasheet - Page 65
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MT48H4M32LFB5-75 IT:K
Manufacturer Part Number
MT48H4M32LFB5-75 IT:K
Description
DRAM Chip Mobile SDRAM 128M-Bit 4Mx32 1.8V 90-Pin VFBGA Tray
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr
Datasheet
1.MT48H8M16LFB4-6K.pdf
(86 pages)
Specifications of MT48H4M32LFB5-75 IT:K
Package
90VFBGA
Density
128 Mb
Address Bus Width
14 Bit
Operating Supply Voltage
1.8 V
Maximum Clock Rate
133 MHz
Maximum Random Access Time
8|5.4 ns
Operating Temperature
-40 to 85 °C
- Current page: 65 of 86
- Download datasheet (3Mb)
Figure 35: READ With Auto Precharge Interrupted by a READ
PDF: 09005aef832ff1ea
128mb_mobile_sdram_y35M.pdf - Rev. G 10/09 EN
Internal
states
Command
Note:
Address
Bank m
Bank n
CLK
DQ
WRITE with auto precharge interrupted by a WRITE (with or without auto precharge)
A WRITE to bank m will interrupt a WRITE on bank n when registered. The precharge to
bank n will begin after
registered. The last valid data WRITE to bank n will be data registered one clock prior to
a WRITE to bank m (see Figure 42 (page 71)).
1. DQM is LOW.
Page active
NOP
T0
READ - AP
Page active
Bank n,
Bank n
T1
Col a
READ with burst of 4
t
WR is met, where
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
T2
CL = 3 (bank n)
NOP
65
READ - AP
Bank m,
T3
Bank m
Col d
Interrupt burst, precharge
READ with burst of 4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
T4
WR begins when the WRITE to bank m is
CL = 3 (bank m)
NOP
t
RP - bank n
D
OUT
T5
NOP
D
OUT
PRECHARGE Operation
T6
NOP
D
©2008 Micron Technology, Inc. All rights reserved.
OUT
Idle
T7
Don’t Care
NOP
t RP - bank m
D
Precharge
OUT
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