MT48H4M32LFB5-75 IT:K Micron Technology Inc, MT48H4M32LFB5-75 IT:K Datasheet - Page 38
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MT48H4M32LFB5-75 IT:K
Manufacturer Part Number
MT48H4M32LFB5-75 IT:K
Description
DRAM Chip Mobile SDRAM 128M-Bit 4Mx32 1.8V 90-Pin VFBGA Tray
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr
Datasheet
1.MT48H8M16LFB4-6K.pdf
(86 pages)
Specifications of MT48H4M32LFB5-75 IT:K
Package
90VFBGA
Density
128 Mb
Address Bus Width
14 Bit
Operating Supply Voltage
1.8 V
Maximum Clock Rate
133 MHz
Maximum Random Access Time
8|5.4 ns
Operating Temperature
-40 to 85 °C
- Current page: 38 of 86
- Download datasheet (3Mb)
Initialization
PDF: 09005aef832ff1ea
128mb_mobile_sdram_y35M.pdf - Rev. G 10/09 EN
Low-power SDRAM devices must be powered up and initialized in a predefined man-
ner. Using initialization procedures other than those specified may result in undefined
operation. After power is simultaneously applied to V
ble (a stable clock is defined as a signal cycling within timing constraints specified for
the clock ball), the device requires a 100μs delay prior to issuing any command other
than a COMMAND INHIBIT or NOP. Starting at some point during this 100μs period
and continuing at least through the end of this period, COMMAND INHIBIT or NOP
commands should be applied.
After the 100μs delay is satisfied by issuing at least one COMMAND INHIBIT or NOP
command, a PRECHARGE command must be issued. All banks must then be pre-
charged, which places the device in the all banks idle state.
When in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO
REFRESH cycles are complete, the device is ready for mode register programming. Be-
cause the mode register powers up in an unknown state, it should be loaded prior to
issuing any operational command.
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
38
Micron Technology, Inc. reserves the right to change products or specifications without notice.
DD
and V
©2008 Micron Technology, Inc. All rights reserved.
DDQ
and the clock is sta-
Initialization
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