MT48H4M32LFB5-75 IT:K Micron Technology Inc, MT48H4M32LFB5-75 IT:K Datasheet - Page 29
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MT48H4M32LFB5-75 IT:K
Manufacturer Part Number
MT48H4M32LFB5-75 IT:K
Description
DRAM Chip Mobile SDRAM 128M-Bit 4Mx32 1.8V 90-Pin VFBGA Tray
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr
Datasheet
1.MT48H8M16LFB4-6K.pdf
(86 pages)
Specifications of MT48H4M32LFB5-75 IT:K
Package
90VFBGA
Density
128 Mb
Address Bus Width
14 Bit
Operating Supply Voltage
1.8 V
Maximum Clock Rate
133 MHz
Maximum Random Access Time
8|5.4 ns
Operating Temperature
-40 to 85 °C
- Current page: 29 of 86
- Download datasheet (3Mb)
READ
Figure 9: READ Command
PDF: 09005aef832ff1ea
128mb_mobile_sdram_y35M.pdf - Rev. G 10/09 EN
Note:
The READ command is used to initiate a burst read access to an active row. The values
on the BA0 and BA1 inputs select the bank; the address provided selects the starting
column location. The value on input A10 determines whether auto precharge is used. If
auto precharge is selected, the row being accessed is precharged at the end of the READ
burst; if auto precharge is not selected, the row remains open for subsequent accesses.
Read data appears on the DQ subject to the logic level on the DQM inputs two clocks
earlier. If a given DQM signal was registered HIGH, the corresponding DQ will be High-
Z two clocks later; if the DQM signal was registered LOW, the DQ will provide valid data.
BA0, BA1
Address
1. EN AP = enable auto precharge, DIS AP = disable auto precharge.
RAS#
CAS#
A10
WE#
CKE
CLK
CS#
1
HIGH
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
Column address
Bank address
DIS AP
EN AP
29
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
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