MT48LC4M16A2P-6:G Micron Technology Inc, MT48LC4M16A2P-6:G Datasheet - Page 58
![DRAM Chip SDRAM 64M-Bit 4Mx16 3.3V 54-Pin TSOP-II Tray](/photos/7/22/72261/557-54-tsop_sml.jpg)
MT48LC4M16A2P-6:G
Manufacturer Part Number
MT48LC4M16A2P-6:G
Description
DRAM Chip SDRAM 64M-Bit 4Mx16 3.3V 54-Pin TSOP-II Tray
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC4M16A2P-75G_TR.pdf
(72 pages)
Specifications of MT48LC4M16A2P-6:G
Density
64 Mb
Maximum Clock Rate
166 MHz
Package
54TSOP-II
Address Bus Width
14 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
5.5 ns
Operating Temperature
0 to 70 °C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
64M (4M x 16)
Speed
167MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
54-TSOP II
Organization
4Mx16
Address Bus
14b
Access Time (max)
5.5ns
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
180mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT48LC4M16A2P-6:G
Manufacturer:
MICRON
Quantity:
3 000
Figure 41:
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
DQML, DQMH
A0–A9, A11
COMMAND
BA0, BA1
DQM /
CLK
CKE
A10
DQ
t CKS
t CMS
READ – With Auto Precharge
t AS
t AS
t AS
ACTIVE
T0
ROW
ROW
BANK
t CMH
t CKH
Notes:
t AH
t AH
t AH
t RCD
t RAS
t RC
t CK
T1
1. For this example, BL = 4, and CL = 2.
2. x16: A8, A9 and A11 = “Don’t Care”
NOP
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
ENABLE AUTO PRECHARGE
t CMS
t CL
COLUMN m 2
BANK
T2
READ
t CMH
t CH
CAS Latency
T3
NOP
t LZ
t AC
58
T4
D
NOP
OUT
t OH
t AC
m
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D
OUT
T5
NOP
m + 1
t OH
t AC
D
OUT
T6
NOP
64Mb: x4, x8, x16 SDRAM
m + 2
t OH
t AC
t RP
©2000 Micron Technology, Inc. All rights reserved.
D
OUT
T7
NOP
Timing Diagrams
m + 3
t OH
t HZ
T8
BANK
ACTIVE
ROW
ROW
DON’T CARE
UNDEFINED