MT48LC4M32B2F5-6:G Micron Technology Inc, MT48LC4M32B2F5-6:G Datasheet - Page 20
![DRAM Chip SDRAM 128M-Bit 4Mx32 3.3V 90-Pin VFBGA Tray](/photos/7/23/72313/mfg557-90-vfbga_sml.jpg)
MT48LC4M32B2F5-6:G
Manufacturer Part Number
MT48LC4M32B2F5-6:G
Description
DRAM Chip SDRAM 128M-Bit 4Mx32 3.3V 90-Pin VFBGA Tray
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC4M32B2P-7G_TR.pdf
(67 pages)
Specifications of MT48LC4M32B2F5-6:G
Density
128 Mb
Maximum Clock Rate
166 MHz
Package
90VFBGA
Address Bus Width
14 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
17|7.5|5.5 ns
Operating Temperature
0 to 70 °C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
128M (4Mx32)
Speed
167MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
90-VFBGA
Organization
4Mx32
Address Bus
14b
Access Time (max)
17/7.5/5.5ns
Operating Supply Voltage (typ)
3.3V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
195mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT48LC4M32B2F5-6:G
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Company:
Part Number:
MT48LC4M32B2F5-6:G TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
BANK/ROW ACTIVATION
Figure 6:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. L 1/09 EN
Activating a Specific Row in a Specific Bank
Upon exiting SELF REFRESH mode, AUTO REFRESH commands must be issued every
15.625µs or less as both SELF REFRESH and AUTO REFRESH utilize the row refresh
counter.
Self refresh is not supported on automotive temperature (AT) devices.
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row
in that bank must be “opened.” This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated. See Figure 6.
After opening a row (issuing an ACTIVE command), a READ or WRITE command may be
issued to that row, subject to the
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
issued. For example, a
results in 2.5 clocks, rounded to 3. This is reflected in Figure 7 on page 21, which covers
any case where 2 <
specification limits from time units to clock cycles.)
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the same bank is defined by
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to different banks is defined by
t
BA0, BA1
RRD.
A0–A11
RAS#
CAS#
WE#
CKE
CLK
CS#
HIGH
t
RCD (MIN)/
ADDRESS
ADDRESS
BANK
ROW
t
RCD specification of 20ns with a 125 MHz clock (8ns period)
DON´T CARE
20
t
t
CK - 3. (The same procedure is used to convert other
RCD specification.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RCD (MIN) should be divided by
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
Register Definition
t
RC.