MT48LC4M32B2F5-6:G Micron Technology Inc, MT48LC4M32B2F5-6:G Datasheet - Page 54
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MT48LC4M32B2F5-6:G
Manufacturer Part Number
MT48LC4M32B2F5-6:G
Description
DRAM Chip SDRAM 128M-Bit 4Mx32 3.3V 90-Pin VFBGA Tray
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC4M32B2P-7G_TR.pdf
(67 pages)
Specifications of MT48LC4M32B2F5-6:G
Density
128 Mb
Maximum Clock Rate
166 MHz
Package
90VFBGA
Address Bus Width
14 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
17|7.5|5.5 ns
Operating Temperature
0 to 70 °C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
128M (4Mx32)
Speed
167MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
90-VFBGA
Organization
4Mx32
Address Bus
14b
Access Time (max)
17/7.5/5.5ns
Operating Supply Voltage (typ)
3.3V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
195mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT48LC4M32B2F5-6:G
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Company:
Part Number:
MT48LC4M32B2F5-6:G TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Figure 37:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. L 1/09 EN
A0–A9, A11
COMMAND
Self Refresh Mode
BA0, BA1
DQM0–3
Notes:
CLK
CKE
A10
DQ
High-Z
Precharge all
t CKS
active banks
t CMS
t
SINGLE BANK
AS
PRECHARGE
ALL BANKS
BANK(S)
T0
1. No maximum time limit for self refresh.
2.
3. As a general rule, any time self refresh is exited, the DRAM may not reenter the self refresh
4. Self refresh mode not supported on automotive temperature (AT) devices.
t CKH
t CMH
t
AH
t CK
3b.
3a. The DRAM has been in self refresh mode for a minimum of 64µs prior to exiting.
3c. At least two AUTO REFRESH commands are preformed during each 15.6µs interval while
t
mode until all rows have been refreshed by the AUTO REFRESH command at the distributed
refresh rate,
XSR requires minimum of two clocks regardless of frequency or timing.
t
the DRAM remains out of the self refresh mode.
XSR is not violated.
t RP
T1
NOP
t CH
Enter self refresh mode
t
REF, or faster. However, the following exceptions are allowed:
t CKS
t CL
REFRESH
AUTO
CLK stable prior to exiting
T2
self refresh mode
> t RAS
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(Restart refresh time base)
Exit self refresh mode
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
Tn + 1
RAS(MAX) applies to non-self refresh mode.
NOP
t XSR
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t CKS
To + 1
To + 2
REFRESH
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
AUTO
DON’T CARE
UNDEFINED
Timing Diagrams