MT48LC4M32B2F5-6:G Micron Technology Inc, MT48LC4M32B2F5-6:G Datasheet - Page 25
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MT48LC4M32B2F5-6:G
Manufacturer Part Number
MT48LC4M32B2F5-6:G
Description
DRAM Chip SDRAM 128M-Bit 4Mx32 3.3V 90-Pin VFBGA Tray
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC4M32B2P-7G_TR.pdf
(67 pages)
Specifications of MT48LC4M32B2F5-6:G
Density
128 Mb
Maximum Clock Rate
166 MHz
Package
90VFBGA
Address Bus Width
14 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
17|7.5|5.5 ns
Operating Temperature
0 to 70 °C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
128M (4Mx32)
Speed
167MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
90-VFBGA
Organization
4Mx32
Address Bus
14b
Access Time (max)
17/7.5/5.5ns
Operating Supply Voltage (typ)
3.3V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
195mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT48LC4M32B2F5-6:G
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Company:
Part Number:
MT48LC4M32B2F5-6:G TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Figure 12:
Figure 13:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. L 1/09 EN
READ-to-WRITE
READ-to-WRITE with Extra Clock Cycle
Notes:
Notes:
COMMAND
1. CL = 3is used for illustration. The READ command may be to any bank, and the WRITE com-
The DQM input is used to avoid I/O contention, as shown in Figures 12 and 13. The
DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE command
(DQM latency is two clocks for output buffers) to suppress data-out from the READ.
Once the WRITE command is registered, the DQs will go High-Z (or remain High-Z),
regardless of the state of the DQM signal; provided the DQM was active on the clock just
prior to the WRITE command that truncated the READ command. If not, the second
WRITE will be an invalid WRITE. For example, if DQM was low during T4 in Figure 13,
then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid.
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 12
shows the case where the clock frequency allows for bus contention to be avoided
without adding a NOP cycle, and Figure 13 shows the case where the additional NOP is
needed.
COMMAND
1. CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE com-
ADDRESS
ADDRESS
mand may be to any bank. If a burst of one is used, then DQM is not required.
mand may be to any bank.
DQM
DQM
CLK
CLK
DQ
DQ
BANK,
COL n
BANK,
T0
COL n
T0
READ
READ
T1
T1
NOP
NOP
T2
T2
NOP
NOP
25
T3
T3
NOP
NOP
D
OUT
t HZ
t HZ
D
t CK
OUT
n
DON’T CARE
n
BANK,
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T4
COL b
WRITE
T4
NOP
D
IN
b
t
DS
DON’T CARE
T5
BANK,
COL b
WRITE
D
IN
b
t
DS
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
Register Definition