JS28F320J3F75A NUMONYX, JS28F320J3F75A Datasheet - Page 25

• Manufacturer Part Number: JS28F320J3F75A
• Description: PARALLEL NOR
• Manufacturer: NUMONYX

Numonyx
Figure 8:
Notes:
1.
2.
Figure 9:
Notes:
1.
2.
March 2010
208032-02
DQ[15:0] [Q]
Address [A]
A[MAX :4] [A]
DQ[15:0] [Q]
BYTE# [F]
WE# [W]
OE # [G]
BYTE # [F]
CEx [E]
A [3:1] [A]
RP# [P ]
WE# [W]
OE # [G]
CE
combination of pins CE0, CE1, and CE2 that disable the device (see
, 64-, 128-Mb” on page 30
When reading the flash array a faster t
query reads, or device identifier reads).
CE
combination of pins CE0, CE1, and CE2 that disable the device (see
, 64-, 128-Mb” on page 30
In this diagram, BYTE# is asserted high.
CEx [E]
RP# [P]
®
X
X
Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
low is defined as the combination of pins CE0, CE1, and CE2 that enable the device. CE
low is defined as the combination of pins CE0, CE1, and CE2 that enable the device. CE
Single-Word Asynchronous Read Waveform
8-Word Asynchronous Page Mode Read
R5
).
).
R6
R6
R2
R11
R5
GLQV
R3
R4
000
R7
R7
(R16) applies. For non-array reads, R4 applies (i.e., Status Register reads,
R2
R3
1
R12
R10
R1
R1
001
R15
2
Table 17, “Chip Enable Truth Table for 32-
Table 17, “Chip Enable Truth Table for 32-
R13
110
7
X
R10
X
111
high is defined as the
high is defined as the
8
R8
R10
R9
R9
Datasheet
R8
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