LH28F640BFHE-PBTL70A Sharp Microelectronics, LH28F640BFHE-PBTL70A Datasheet - Page 28

• Manufacturer Part Number: LH28F640BFHE-PBTL70A
• Description: Flash Mem Parallel 3V/3.3V 64M-Bit 4M x 16 70ns 48-Pin TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F640BFHE-PBTL70A

• Package: 48TSOP
• Cell Type: NOR
• Density: 64 Mb
• Architecture: Sectored
• Block Organization: Asymmetrical
• Location Of Boot Block: Bottom
• Typical Operating Supply Voltage: 3|3.3 V
• Sector Size: 8KByte x 8|64KByte x 127
• Timing Type: Asynchronous
• Operating Temperature: -40 to 85 °C
• Interface Type: Parallel

1.2.5 AC Characteristics - Write Operations
NOTES:
1. The timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program and
2. A write operation can be initiated and terminated with either CE# or WE#.
3. Sampled, not 100% tested.
4. Write pulse width (t
5. Write pulse width high (t
6. V
7. t
8. Refer to Table 6 for valid address and data for block erase, full chip erase, (page buffer) program, OTP program or lock bit
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AVAV
PHWL
ELWL
WLWH
DVWH
AVWH
WHEH
WHDX
WHAX
WHWL
SHWH
VVWH
WHGL
QVSL
QVVL
WHR0
OTP program operations are the same as during read-only operations. Refer to AC Characteristics for read-only
operations.
CE# or WE# (whichever goes high first). Hence, t
edge of CE# or WE# (whichever goes low last). Hence, t
program success (SR.1/3/4/5=0).
configuration.
WHR0
PP
Symbol
should be held at V
(t
(t
(t
(t
(t
(t
(t
(t
(t
(t
(t
(t
(t
WLEL
PHEL
EHR0
(t
AVEH
EHWH
SHEH
EHGL
ELEH
DVEH
EHDX
EHAX
VVEH
EHEL
EHR0
)
)
)
)
)
)
)
)
)
)
)
)
)
) after the Read Query or Read Identifier Codes/OTP command=t
Write Cycle Time
RST# High Recovery to WE# (CE#) Going Low
CE# (WE#) Setup to WE# (CE#) Going Low
WE# (CE#) Pulse Width
Data Setup to WE# (CE#) Going High
Address Setup to WE# (CE#) Going High
CE# (WE#) Hold from WE# (CE#) High
Data Hold from WE# (CE#) High
Address Hold from WE# (CE#) High
WE# (CE#) Pulse Width High
WP# High Setup to WE# (CE#) Going High
V
Write Recovery before Read
WP# High Hold from Valid SRD
V
WE# (CE#) High to SR.7 Going "0"
WP
PP
PP
) is defined from the falling edge of CE# or WE# (whichever goes low last) to the rising edge of
Setup to WE# (CE#) Going High
Hold from Valid SRD
PP
WPH
=V
) is defined from the rising edge of CE# or WE# (whichever goes high first) to the falling
PPH1/2
until determination of block erase, full chip erase, (page buffer) program or OTP
V
CC
Parameter
=2.7V-3.6V, T
WP
(1), (2)
LHF64FG8
=t
WLWH
WPH
A
=-40°C to +85°C
=t
=t
WHWL
ELEH
=t
=t
WLEH
EHEL
=t
=t
ELWH
WHEL
AVQV
Notes
3, 6
3, 6
3, 7
3
4
8
8
5
3
3
.
+100ns.
=t
EHWL
.
Min.
150
200
70
55
40
55
15
30
0
0
0
0
0
0
0
t
AVQV
Max.
50
+
Rev. 2.45
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25