LH28F640BFHE-PBTL70A Sharp Microelectronics, LH28F640BFHE-PBTL70A Datasheet - Page 45

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LH28F640BFHE-PBTL70A

Manufacturer Part Number
LH28F640BFHE-PBTL70A
Description
Flash Mem Parallel 3V/3.3V 64M-Bit 4M x 16 70ns 48-Pin TSOP
Manufacturer
Sharp Microelectronics
Datasheet

Specifications of LH28F640BFHE-PBTL70A

Package
48TSOP
Cell Type
NOR
Density
64 Mb
Architecture
Sectored
Block Organization
Asymmetrical
Location Of Boot Block
Bottom
Typical Operating Supply Voltage
3|3.3 V
Sector Size
8KByte x 8|64KByte x 127
Timing Type
Asynchronous
Operating Temperature
-40 to 85 °C
Interface Type
Parallel

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Part Number:
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Manufacturer:
SHARP
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A-1 RECOMMENDED OPERATING CONDITIONS
A-1.1 At Device Power-Up
If the timing in the figure is ignored, the device may not operate correctly.
described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in
the next page.
AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up.
For the AC specifications t
ADDRESS
*1 To prevent the unwanted writes, system designers should consider the design, which applies V
V
(V
DATA
(RST#)
CCW
to 0V during read operations and V
See the application note AP-007-SW-E for details.
WE#
WP#
RP#
PP
CE#
OE#
V
)
CC
*1
(W)
(D/Q)
(V)
(E)
(G)
(P)
(S)
(A)
V
V
(V
GND
CC
GND
CCWH1/2
V
V
V
V
V
V
V
V
V
V
V
PPH1/2
V
V
V
(min)
OH
OL
IH
IH
IH
IH
IH
IH
IL
IL
IL
IL
IL
IL
)
VR
, t
R
, t
t
VR
F
Figure A-1. AC Timing at Device Power-Up
in the figure, refer to the next page. See the “ELECTRICAL SPECIFICATIONS“
CCWH1/2
t
2VPH
(V
PPH1/2
) during write or erase operations.
High Z
t
R
or
t
F
t
PHQV
t
F
t
AVQV
Address
t
Valid
F
t
ELQV
t
GLQV
CCW
Output
Valid
(V
PP
)
t
t
t
Rev. 1.10
R
R
R
or
t
F
i

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