P87C51FB-4N NXP Semiconductors, P87C51FB-4N Datasheet - Page 19

• Manufacturer Part Number: P87C51FB-4N
• Description: MCU 8-Bit 87C 80C51 CISC 16KB EPROM 3.3V/5V 40-Pin PDIP Tube
• Manufacturer: NXP Semiconductors

Specifications of P87C51FB-4N

• Program Memory Size: 16 KB
• Package: 40PDIP
• Device Core: 80C51
• Family Name: 87C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 32
• Interface Type: UART
• Number Of Timers: 3
• Ram Size: 256 Byte
• Program Memory Type: EPROM
• Operating Temperature: 0 to 70 °C
• Controller Family/series: (8051) 8052
• No. Of I/o's: 32
• Ram Memory Size: 265Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Oscillator Type: External Only

Philips Semiconductors
Enhanced UART
The UART operates in all of the usual modes that are described in
the first section of Data Handbook IC20, 80C51-Based 8-Bit
Microcontrollers . In addition the UART can perform framing error
detect by looking for missing stop bits, and automatic address
recognition. The UART also fully supports multiprocessor
communication as does the standard 80C51 UART.
When used for framing error detect the UART looks for missing stop
bits in the communication. A missing bit will set the FE bit in the
SCON register. The FE bit shares the SCON.7 bit with SM0 and the
function of SCON.7 is determined by PCON.6 (SMOD0) (see
Figure 7). If SMOD0 is set then SCON.7 functions as FE. SCON.7
functions as SM0 when SMOD0 is cleared. When used as FE
SCON.7 can only be cleared by software. Refer to Figure 8.
Automatic Address Recognition
Automatic Address Recognition is a feature which allows the UART
to recognize certain addresses in the serial bit stream by using
hardware to make the comparisons. This feature saves a great deal
of software overhead by eliminating the need for the software to
examine every serial address which passes by the serial port. This
feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART
modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be
automatically set when the received byte contains either the “Given”
address or the “Broadcast” address. The 9 bit mode requires that
the 9th information bit is a 1 to indicate that the received information
is an address and not data. Automatic address recognition is shown
in Figure 9.
The 8 bit mode is called Mode 1. In this mode the RI flag will be set
if SM2 is enabled and the information received has a valid stop bit
following the 8 address bits and the information is either a Given or
Broadcast address.
Mode 0 is the Shift Register mode and SM2 is ignored.
Using the Automatic Address Recognition feature allows a master to
selectively communicate with one or more slaves by invoking the
Given slave address or addresses. All of the slaves may be
contacted by using the Broadcast address. Two special Function
Registers are used to define the slave’s address, SADDR, and the
address mask, SADEN. SADEN is used to define which bits in the
SADDR are to b used and which bits are “don’t care”. The SADEN
mask can be logically ANDed with the SADDR to create the “Given”
address which the master will use for addressing each of the slaves.
Use of the Given address allows multiple slaves to be recognized
while excluding others. The following examples will help to show the
versatility of this scheme:
Slave 0
2000 Aug 07
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
SADDR =
SADEN =
Given
=
1100 0000
1111 1101
1100 00X0
19
uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and
cares”. This effectively disables the Automatic Addressing mode and
Slave 1
In the above example SADDR is the same and the SADEN data is
used to differentiate between the two slaves. Slave 0 requires a 0 in
bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is
ignored. A unique address for Slave 0 would be 1100 0010 since
slave 1 requires a 0 in bit 1. A unique address for slave 1 would be
1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be
selected at the same time by an address which has bit 0 = 0 (for
slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed
with 1100 0000.
In a more complex system the following could be used to select
slaves 1 and 2 while excluding slave 0:
Slave 0
Slave 1
Slave 2
In the above example the differentiation among the 3 slaves is in the
lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be
it can be uniquely addressed by 1110 and 0101. Slave 2 requires
that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0
and 1 and exclude Slave 2 use address 1110 0100, since it is
necessary to make bit 2 = 1 to exclude slave 2.
The Broadcast Address for each slave is created by taking the
logical OR of SADDR and SADEN. Zeros in this result are trended
as don’t-cares. In most cases, interpreting the don’t-cares as ones,
the broadcast address will be FF hexadecimal.
Upon reset SADDR (SFR address 0A9H) and SADEN (SFR
address 0B9H) are leaded with 0s. This produces a given address
of all “don’t cares” as well as a Broadcast address of all “don’t
allows the microcontroller to use standard 80C51 type UART drivers
which do not make use of this feature.
SADDR =
SADEN =
Given
SADDR =
SADEN =
Given
SADDR =
SADEN =
Given
SADDR =
SADEN =
Given
8XC51RA+/RB+/RC+/RD+/80C51RA+
=
=
=
=
8XC51FA/FB/FC/80C51FA
1100 0000
1111 1110
1100 000X
1100 0000
1111 1001
1100 0XX0
1110 0000
1111 1010
1110 0X0X
1110 0000
1111 1100
1110 00XX
Product specification
8XC54/58