XC2S300E-6PQ208I Xilinx Inc, XC2S300E-6PQ208I Datasheet - Page 10

• Manufacturer Part Number: XC2S300E-6PQ208I
• Description: FPGA Spartan®-IIE Family 300K Gates 6912 Cells 357MHz 0.15um Technology 1.8V 208-Pin PQFP
• Manufacturer: Xilinx Inc

Specifications of XC2S300E-6PQ208I

• Package: 208PQFP
• Family Name: Spartan®-IIE
• Device Logic Cells: 6912
• Device Logic Units: 1536
• Device System Gates: 300000
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 146
• Ram Bits: 65536

Spartan-IIE FPGA Family: Functional Description
Table 3: Standards Supported by I/O (Typical Values)
10
LVTTL (2-24 mA)
LVCMOS2
LVCMOS18
PCI (3V,
33 MHz/66 MHz)
GTL
GTL+
HSTL Class I
HSTL Class III
HSTL Class IV
SSTL3 Class I
and II
SSTL2 Class I
and II
CTT
AGP
LVDS, Bus LVDS
LVPECL
I/O Standard
Reference
Voltage
(V
Input
0.75
1.25
1.32
N/A
N/A
N/A
N/A
N/A
N/A
0.8
1.0
0.9
0.9
1.5
1.5
TFF
OFF
IFF
REF
)
Voltage
(V
Input
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.3
2.5
1.8
3.3
CCO
)
Figure 4: Spartan-IIE Input/Output Block (IOB)
Voltage
Source
Output
(V
N/A
N/A
3.3
2.5
1.8
3.3
1.5
1.5
1.5
3.3
2.5
3.3
3.3
2.5
3.3
CCO
)
Termination
Voltage
Board
(V
0.75
1.25
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.2
1.5
1.5
1.5
1.5
1.5
TT
)
www.xilinx.com
Input/Output Block
The Spartan-IIE FPGA IOB, as seen in
inputs and outputs that support a wide variety of I/O signal-
ing standards. These high-speed inputs and outputs are
capable of supporting various state of the art memory and
bus interfaces. The default standard is LVTTL.
several of the standards which are supported along with the
required reference (V
nation (V
more details on the I/O standards and termination applica-
tion examples, see XAPP179, "Using SelectIO Interfaces in
Spartan-II and Spartan-IIE FPGAs."
The three IOB registers function either as edge-triggered
D-type flip-flops or as level-sensitive latches. Each IOB has
a clock signal (CLK) shared by the three registers and inde-
pendent Clock Enable (CE) signals for each register.
In addition to the CLK and CE control signals, the three reg-
isters share a Set/Reset (SR). For each register, this signal
can be independently configured as a synchronous Set, a
synchronous Reset, an asynchronous Preset, or an asyn-
chronous Clear.
A feature not shown in the block diagram, but controlled by
the software, is polarity control. The input and output buffers
and all of the IOB control signals have independent polarity
controls.
TT
) voltages needed to meet the standard. For
REF
), output (V
DS077-2 (v2.3) June 18, 2008
CCO
Product Specification
) and board termi-
Figure
Table 3
4, features
lists
R