XC2S300E-6PQ208I Xilinx Inc, XC2S300E-6PQ208I Datasheet - Page 44
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XC2S300E-6PQ208I
Manufacturer Part Number
XC2S300E-6PQ208I
Description
FPGA Spartan®-IIE Family 300K Gates 6912 Cells 357MHz 0.15um Technology 1.8V 208-Pin PQFP
Manufacturer
Xilinx Inc
Datasheet
1.XC2S50E-6TQG144C.pdf
(108 pages)
Specifications of XC2S300E-6PQ208I
Package
208PQFP
Family Name
Spartan®-IIE
Device Logic Cells
6912
Device Logic Units
1536
Device System Gates
300000
Maximum Internal Frequency
357 MHz
Typical Operating Supply Voltage
1.8 V
Maximum Number Of User I/os
146
Ram Bits
65536
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC2S300E-6PQ208I
Manufacturer:
XILINX
Quantity:
898
Spartan-IIE FPGA Family: DC and Switching Characteristics
44
Output Jitter: the difference between an ideal
reference clock edge and the actual design.
Period Tolerance: the allowed input clock period change in nanoseconds.
Ideal Period
Actual Period
T
CLKIN
=
F CLKIN
1
Figure 22: Period Tolerance and Clock Jitter
www.xilinx.com
T CLKIN + T IPTOL
Phase Offset and Maximum Phase Difference
_
+/- Jitter
+ Maximum
+ Phase Offset
Phase Difference
DS077-3 (v2.3) June 18, 2008
Product Specification
DS001_52_090800
R