XC2S300E-6PQ208I Xilinx Inc, XC2S300E-6PQ208I Datasheet - Page 34
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XC2S300E-6PQ208I
Manufacturer Part Number
XC2S300E-6PQ208I
Description
FPGA Spartan®-IIE Family 300K Gates 6912 Cells 357MHz 0.15um Technology 1.8V 208-Pin PQFP
Manufacturer
Xilinx Inc
Datasheet
1.XC2S50E-6TQG144C.pdf
(108 pages)
Specifications of XC2S300E-6PQ208I
Package
208PQFP
Family Name
Spartan®-IIE
Device Logic Cells
6912
Device Logic Units
1536
Device System Gates
300000
Maximum Internal Frequency
357 MHz
Typical Operating Supply Voltage
1.8 V
Maximum Number Of User I/os
146
Ram Bits
65536
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC2S300E-6PQ208I
Manufacturer:
XILINX
Quantity:
898
Spartan-IIE FPGA Family: DC and Switching Characteristics
LVDS DC Specifications
LVPECL DC Specifications
These values are valid at the output of the source termina-
tion pack shown under LVPECL, with a 100Ω differential
load only. The V
34
Notes:
1.
2.
Input/Output
HSTL I
HSTL III
HSTL IV
SSTL3 I
SSTL3 II
SSTL2 I
SSTL2 II
CTT
AGP
Symbol
V
V
V
V
Standard
V
V
V
ODIFF
IDIFF
OCM
V
Tested according to the relevant specifications.
CCO
ICM
OH
OL
OL
and V
Differential input voltage
Supply voltage
Output High voltage for Q and Q
Output Low voltage for Q and Q
Differential output voltage (Q – Q),
Q = High or (Q – Q), Q = High
Output common-mode voltage
Differential input voltage (Q – Q),
Q = High or (Q – Q), Q = High
Input common-mode voltage
OH
DC Parameter
for lower drive currents are sample tested.
OH
V, Min
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
V
V
V
V
CCO
V
OH
OL
levels are 200 mV below standard
IH
IL
Description
V
IL
V
V
V
V
V
V
V
V
V
REF
REF
REF
REF
REF
REF
REF
REF
REF
V, Max
– 0.1
– 0.1
– 0.1
– 0.2
– 0.2
– 0.2
– 0.2
– 0.2
– 0.2
V
V
V
V
V
V
V
V
V
REF
REF
REF
REF
REF
REF
REF
REF
REF
V, Min
0.96
1.49
0.86
Min
1.8
0.3
Common-mode input voltage = 1.25 V
+ 0.1
+ 0.1
+ 0.1
+ 0.2
+ 0.2
+ 0.2
+ 0.2
+ 0.2
+ 0.2
Differential input voltage = ±350 mV
R
R
R
R
T
T
T
T
www.xilinx.com
= 100Ω across Q and Q signals
= 100Ω across Q and Q signals
= 100Ω across Q and Q signals
= 100Ω across Q and Q signals
3.0
V
IH
2.125
Max
2.11
1.27
2.72
V, Max
-
Conditions
LVPECL levels and are compatible with devices tolerant of
lower common-mode ranges. The following table summa-
rizes the DC output specifications of LVPECL.
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
1.92
1.06
1.49
0.86
Min
0.3
V
V
V
V
V
10% V
REF
REF
REF
REF
REF
V, Max
V
3.3
0.4
0.4
0.4
OL
– 0.61 V
– 0.6
– 0.8
– 0.8
– 0.4
CCO
2.125
Max
2.28
1.43
2.72
-
V
V
V
V
V
V
V
90% V
REF
CCO
CCO
CCO
REF
REF
REF
REF
2.375
1.125
V, Min
1.25
Min
250
100
0.9
0.2
V
OH
+ 0.61
+ 0.6
+ 0.8
+ 0.8
+ 0.4
– 0.4
– 0.4
– 0.4
2.13
1.30
1.49
0.86
Min
0.3
CCO
DS077-3 (v2.3) June 18, 2008
1.425
1.075
1.25
1.25
Typ
350
350
2.5
3.6
Product Specification
Note (2)
15.2
2.125
mA
I
7.6
24
48
16
Max
2.41
1.57
2.72
OL
8
8
8
2.625
1.375
-
Max
1.25
450
1.6
2.2
-
Note (2)
–15.2
Units
–7.6
Units
–16
mA
I
–8
–8
–8
–8
–8
OH
mV
mV
V
V
V
V
V
V
V
V
V
V
V
R