XC2V250-4CS144I Xilinx Inc, XC2V250-4CS144I Datasheet - Page 35

• Manufacturer Part Number: XC2V250-4CS144I
• Description: FPGA Virtex-II™ Family 250K Gates 3456 Cells 650MHz 0.15um/0.12um (CMOS) Technology 1.5V 144-Pin CSBGA
• Manufacturer: Xilinx Inc

Specifications of XC2V250-4CS144I

• Package: 144CSBGA
• Family Name: Virtex-II™
• Device Logic Units: 3456
• Device System Gates: 250000
• Number Of Registers: 3072
• Maximum Internal Frequency: 650 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 92
• Ram Bits: 442368

Global Clock Multiplexer Buffers
Virtex-II devices have 16 clock input pins that can also be
used as regular user I/Os. Eight clock pads are on the top
edge of the device, in the middle of the array, and eight are
on the bottom edge, as illustrated in
The global clock multiplexer buffer represents the input to
dedicated low-skew clock tree distribution in Virtex-II
devices. Like the clock pads, eight global clock multiplexer
buffers are on the top edge of the device and eight are on
the bottom edge.
Each global clock buffer can either be driven by the clock
pad to distribute a clock directly to the device, or driven by
the Digital Clock Manager (DCM), discussed in
Manager (DCM), page
be driven by local interconnects. The DCM has clock out-
put(s) that can be connected to global clock buffer inputs, as
shown in
DS031-2 (v3.5) November 5, 2007
Product Specification
Figure
R
39.
Multiplier Blocks
29. Each global clock buffer can also
Figure 37: Multipliers (2-column, 4-column, and 6-column)
Figure
38.
Digital Clock
Multiplier Blocks
www.xilinx.com
Virtex-II Platform FPGAs: Functional Description
Multiplier Blocks
Figure 38: Virtex-II Clock Pads
Virtex-II
Device
8 clock pads
8 clock pads
DS031_39_101000
DS031_42_022305
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