XC2V250-4CS144I Xilinx Inc, XC2V250-4CS144I Datasheet - Page 65

• Manufacturer Part Number: XC2V250-4CS144I
• Description: FPGA Virtex-II™ Family 250K Gates 3456 Cells 650MHz 0.15um/0.12um (CMOS) Technology 1.5V 144-Pin CSBGA
• Manufacturer: Xilinx Inc

Specifications of XC2V250-4CS144I

• Package: 144CSBGA
• Family Name: Virtex-II™
• Device Logic Units: 3456
• Device System Gates: 250000
• Number Of Registers: 3072
• Maximum Internal Frequency: 650 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 92
• Ram Bits: 442368

I/O
Input Delay Measurements
Table 18
Table 18: Input Delay Measurement Methodology
DS031-3 (v3.5) November 5, 2007
Product Specification
Notes:
1.
2.
3.
4.
5.
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVCMOS (Low-Voltage CMOS), 3.3V
LVCMOS, 2.5V
LVCMOS, 1.8V
LVCMOS, 1.5V
PCI (Peripheral Component Interface), 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
PCI-X, 133 MHz, 3.3V
GTL (Gunning Transceiver Logic)
GTL Plus
HSTL (High-Speed Transceiver Logic), Class I & II
HSTL, Class III & IV
HSTL, Class I & II, 1.8V
HSTL, Class III & IV, 1.8V
SSTL (Stub Terminated Transceiver Logic), Class I & II, 3.3V
SSTL, Class I & II, 2.5V
SSTL, Class I & II, 1.8V
AGP-2X/AGP (Accelerated Graphics Port)
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDS, 3.3V
LVDSEXT (LVDS Extended Mode), 2.5V
LVDSEXT, 3.3V
ULVDS (Ultra LVDS), 2.5V
LDT (HyperTransport), 2.5V
LVPECL (Low-Voltage Positive Electron-Coupled Logic), 3.3V
Standard Adjustment Measurement Methodology
Input delay measurement methodology parameters for LVDCI and HSLVDCI are the same as for LVCMOS standards of the same voltage. Parameters
for all other DCI standards are the same as for the corresponding non-DCI standards.
Input waveform switches between V
Measurements are made at typical, minimum, and maximum V
listed are typical. See
Input voltage level from which measurement starts.
Note that this is an input voltage reference that bears no relation to the V
shows the test setup parameters used for measuring Input standard adjustments (see
R
Description
Virtex-II Platform FPGA User Guide
L
and V
H
.
for min/max specifications.
www.xilinx.com
REF
HSTL_III_18, HSTL_IV_18
HSTL_I_18, HSTL_II_18
SSTL18_I, SSTL18_II
values. Reported delays reflect worst case of these measurements. V
SSTL2_I, SSTL2_II
HSTL_III, HSTL_IV
SSTL3_I, SSTL3_II
Virtex-II Platform FPGAs: DC and Switching Characteristics
HSTL_I, HSTL_II
IOSTANDARD
LVDSEXT_25
LVDSEXT_33
LVPECL_33
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
ULVDS_25
Attribute
REF
LVDS_25
LVDS_33
PCI33_3
PCI66_3
LDT_25
LVTTL
GTLP
PCIX
AGP
GTL
/ V
MEAS
parameters found in IBIS models and/or noted in
V
V
(0.2 xV
1.2 – 0.125
1.2 – 0.125
1.2 – 0.125
1.2 – 0.125
0.6 – 0.125
0.6 – 0.125
V
V
V
V
V
V
V
REF
REF
1.6 – 0.3
REF
REF
REF
REF
REF
REF
REF
V
V
REF
L
0
0
0
0
0
– 1.00
– 0.75
– 0.2
– 0.2
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
(1,2)
Per PCI-X Specification
CCO
Per PCI Specification
Per PCI Specification
–
)
V
V
(0.2 xV
1.2 + 0.125
1.2 + 0.125
0.6 + 0.125
0.6 + 0.125
1.2 + 0.125
1.2 + 0.125
V
V
V
V
V
V
V
REF
REF
1.6 + 0.3
Table 15, page
REF
REF
REF
REF
REF
REF
REF
V
V
REF
3.0
2.5
1.8
1.5
3.3
H
+ 1.00
+ 0.75
+ 0.2
+ 0.2
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.5
(1,2)
CCO
+
)
V
(1,4,5)
V
V
V
V
V
V
V
V
V
V
1.65
1.25
0.75
MEAS
1.4
0.9
1.2
1.2
1.2
1.2
0.6
0.6
1.6
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
Module 3 of 4
11).
Figure
REF
(1,3,5)
V
Spec
AGP
values
0.80
0.75
0.90
0.90
1.08
1.25
0.90
1.0
1.5
REF
1.
–
–
–
–
–
–
–
–
17