XC2V250-4CS144I Xilinx Inc, XC2V250-4CS144I Datasheet - Page 80

• Manufacturer Part Number: XC2V250-4CS144I
• Description: FPGA Virtex-II™ Family 250K Gates 3456 Cells 650MHz 0.15um/0.12um (CMOS) Technology 1.5V 144-Pin CSBGA
• Manufacturer: Xilinx Inc

Specifications of XC2V250-4CS144I

• Package: 144CSBGA
• Family Name: Virtex-II™
• Device Logic Units: 3456
• Device System Gates: 250000
• Number Of Registers: 3072
• Maximum Internal Frequency: 650 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 92
• Ram Bits: 442368

Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, Without DCM
Table 35: Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, Without DCM
DS031-3 (v3.5) November 5, 2007
Product Specification
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
2. Output timing is measured at 50% V
LVTTL Global Clock Input to Output Delay using
Output flip-flop, 12 mA, Fast Slew Rate, without DCM.
For data output with different standards, adjust the
delays with the values shown in
Characteristics Standard Adjustments, page
Global Clock and OFF without DCM
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
R
Description
IOB Output Switching
CC
threshold with test setup shown in
14.
www.xilinx.com
Symbol
T
ICKOF
Virtex-II Platform FPGAs: DC and Switching Characteristics
XC2V1000
XC2V1500
XC2V2000
XC2V3000
XC2V4000
XC2V6000
XC2V8000
XC2V250
XC2V500
Figure
XC2V40
XC2V80
Device
1. For other I/O standards, see
3.46
3.62
3.79
3.85
4.02
4.16
4.30
4.49
4.82
5.19
-6
Speed Grade
3.58
3.58
3.88
3.88
4.28
4.28
4.43
4.64
4.99
5.38
6.09
-5
Table
3.69
3.69
4.47
4.47
4.62
4.62
5.10
5.34
5.74
5.93
7.00
-4
Module 3 of 4
19.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
32