XC2V250-4CS144I Xilinx Inc, XC2V250-4CS144I Datasheet - Page 95

• Manufacturer Part Number: XC2V250-4CS144I
• Description: FPGA Virtex-II™ Family 250K Gates 3456 Cells 650MHz 0.15um/0.12um (CMOS) Technology 1.5V 144-Pin CSBGA
• Manufacturer: Xilinx Inc

Specifications of XC2V250-4CS144I

• Package: 144CSBGA
• Family Name: Virtex-II™
• Device Logic Units: 3456
• Device System Gates: 250000
• Number Of Registers: 3072
• Maximum Internal Frequency: 650 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 92
• Ram Bits: 442368

Pin Definitions
Table 4
Table 4: Virtex-II Pin Definitions
DS031-4 (v3.5) November 5, 2007
Product Specification
User I/O Pins
IO_LXXY_#
Dual-Function Pins
IO_LXXY_#/ZZZ
With /ZZZ:
D0/DIN, D1, D2,
D3, D4, D5, D6,
D7
CS_B
RDWR_B
BUSY/DOUT
INIT_B
GCLKx (S/P)
VRP
VRN
ALT_VRP
ALT_VRN
V
Dedicated Pins
CCLK
REF
Pin Name
provides a description of each pin type listed in Virtex-II pinout tables.
R
(1)
Input/Output/
Bidirectional
Input/Output
Input
Input
Output
Bidirectional
(open-drain)
Input/Output
Input
Input
Input
Input
Input
Input/Output
Direction
All user I/O pins are capable of differential signalling and can implement LVDS,
ULVDS, BLVDS, LVPECL, or LDT pairs. Each user I/O is labeled “IO_LXXY_#”, where:
The dual-function pins are labelled “IO_LXXY_#/ZZZ”, where ZZZ can be one of the
following pins:
Per Bank - VRP, VRN, or VREF
Globally - GCLKX(S/P), BUSY/DOUT, INIT_B, D0/DIN – D7, RDWR_B, or CS_B
•
•
In SelectMAP mode, this is the active-low Chip Select signal. The pin becomes a user
I/O after configuration, unless the SelectMAP port is retained.
In SelectMAP mode, this is the active-low Write Enable signal. The pin becomes a user
I/O after configuration, unless the SelectMAP port is retained.
•
•
When Low, this pin indicates that the configuration memory is being cleared. When
held Low, the start of configuration is delayed. During configuration, a Low on this
output indicates that a configuration data error has occurred. The pin becomes a user
I/O after configuration.
These are clock input pins that connect to Global Clock Buffers. These pins become
regular user I/Os when not needed for clocks.
This pin is for the DCI voltage reference resistor of P transistor (per bank).
This pin is for the DCI voltage reference resistor of N transistor (per bank).
This is the alternative pin for the DCI voltage reference resistor of P transistor.
This is the alternative pin for the DCI voltage reference resistor of N transistor.
These are input threshold voltage pins. They become user I/Os when an external
threshold voltage is not needed (per bank).
Configuration clock. Output in Master mode or Input in Slave mode.
IO indicates a user I/O pin.
LXXY indicates a differential pair, with XX a unique pair in the bank and Y = P/N for
the positive and negative sides of the differential pair.
# indicates the bank number (0 through 7)
In SelectMAP mode, D0 through D7 are configuration data pins. These pins
become user I/Os after configuration, unless the SelectMAP port is retained.
In bit-serial modes, DIN (D0) is the single-data input. This pin becomes a user I/O
after configuration.
In SelectMAP mode, BUSY controls the rate at which configuration data is
loaded. The pin becomes a user I/O after configuration, unless the SelectMAP
port is retained.
In bit-serial modes, DOUT provides preamble and configuration data to
downstream devices in a daisy-chain. The pin becomes a user I/O after
configuration.
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Description
Virtex-II Platform FPGAs: Pinout Information
Module 4 of 4
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