XC2VP7-5FFG672C Xilinx Inc, XC2VP7-5FFG672C Datasheet - Page 83
![FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA](/photos/6/74/67431/xc2vp7-5ffg672c_sml.jpg)
XC2VP7-5FFG672C
Manufacturer Part Number
XC2VP7-5FFG672C
Description
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet
1.XC2VP20-5FGG676C.pdf
(430 pages)
Specifications of XC2VP7-5FFG672C
Package
672FCBGA
Family Name
Virtex-II ProÂ
Device Logic Units
11088
Number Of Registers
9856
Maximum Internal Frequency
1050 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
396
Ram Bits
811008
Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1370
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC2VP7-5FFG672C
Manufacturer:
XILINX
Quantity:
745
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Table 17: Processor Block Switching Characteristics
Table 18: Processor Block PLB Switching Characteristics
DS083 (v4.7) November 5, 2007
Product Specification
Setup and Hold Relative to Clock
(CPMC405CLOCK)
Clock to Out
Clock
Setup and Hold Relative to Clock (PLBCLK)
Clock to Out
Device Control Register Bus control inputs
Device Control Register Bus data inputs
Clock and Power Management control inputs
Reset control inputs
Debug control inputs
Trace control inputs
External Interrupt Controller control inputs
Device Control Register Bus control outputs
Device Control Register Bus address outputs
Device Control Register Bus data outputs
Clock and Power Management control outputs
Reset control outputs
Debug control outputs
Trace control outputs
CPMC405CLOCK minimum pulse width, high
CPMC405CLOCK minimum pulse width, low
Processor Local Bus(ICU/DCU) control inputs
Processor Local Bus (ICU/DCU) data inputs
Processor Local Bus(ICU/DCU) control outputs
Processor Local Bus(ICU/DCU) address bus outputs
Processor Local Bus(ICU/DCU) data bus outputs
R
Description
Description
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
T
T
T
T
T
T
T
T
T
PCCK
PCCK
PDCK
PCCK
PCCK
PCCK
www.xilinx.com
PCCK
PCCK
PDCK
T
T
T
T
T
T
T
_DCR/T
_DCR/T
_CPM/T
_DBG/T
_TRC/T
T
T
_RST/T
T
PCKCO
PCKDO
PCKCO
PCKCO
PCKAO
PCKCO
PCKCO
_PLB/T
_PLB/T
_EIC/T
PCKCO
PCKDO
PCKAO
Symbol
Symbol
T
T
CPWH
CPWL
_DCR
_DCR
_DCR
_CPM
_DBG
_TRC
_RST
_PLB
_PLB
_PLB
PCKC
PCKD
PCKC
PCKC
PCKC
PCKC
PCKC
PCKC
PCKD
_DCR
_DCR
_CPM
_RST
_DBG
_TRC
_EIC
_PLB
_PLB
0.38/–0.18
0.65/–0.01
1.37/–0.41
0.57/–0.22
0.16/ 0.03
0.16/ 0.03
0.27/ 0.30
0.98/ 0.18
0.62/ 0.16
1.32
1.72
1.76
1.26
1.32
1.94
1.35
1.25
1.25
1.34
1.16
1.44
-7
-7
Speed Grade
Speed Grade
0.44/–0.20
0.75/–0.01
1.57/–0.48
0.66/–0.25
0.19/ 0.03
0.19/ 0.03
0.31/ 0.35
1.12/ 0.21
0.71/ 0.18
1.52
1.98
2.02
1.45
1.51
2.22
1.56
1.42
1.42
1.54
1.34
1.65
-6
-6
0.48/–0.23
0.82/–0.02
1.73/–0.52
0.72/–0.27
0.20/ 0.03
0.20/ 0.03
0.34/ 0.38
1.23/ 0.23
0.78/ 0.20
1.67
2.17
2.22
1.59
1.66
2.44
1.71
1.66
1.66
1.69
1.47
1.81
-5
-5
Module 3 of 4
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
Units
Units
12
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