XC3S1600E-4FGG484I Xilinx Inc, XC3S1600E-4FGG484I Datasheet - Page 131
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XC3S1600E-4FGG484I
Manufacturer Part Number
XC3S1600E-4FGG484I
Description
FPGA Spartan®-3E Family 1.6M Gates 33192 Cells 572MHz 90nm (CMOS) Technology 1.2V 484-Pin FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S1600E-4FGG484I
Package
484FBGA
Family Name
Spartan®-3E
Device Logic Cells
33192
Device Logic Units
3688
Device System Gates
1600000
Number Of Registers
29504
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
376
Ram Bits
663552
Number Of Logic Elements/cells
33192
Number Of Labs/clbs
3688
Total Ram Bits
663552
Number Of I /o
376
Number Of Gates
1600000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-XA3S1600E-UNI-G - KIT DEVELOPMENT AUTOMOTIVE ECU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
XC3S1600E-4FGG484I
Manufacturer:
XILINX
Quantity:
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Part Number:
XC3S1600E-4FGG484I
Manufacturer:
XILINX
Quantity:
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Part Number:
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Quantity:
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Part Number:
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XILINX/赛灵思
Quantity:
20 000
Table 92: Timing for the IOB Output Path
DS312-3 (v3.8) August 26, 2009
Product Specification
Notes:
1.
2.
3.
Clock-to-Output Times
T
Propagation Times
T
T
Set/Reset Times
T
T
IOCKP
IOOP
IOOLP
IOSRP
IOGSRQ
Symbol
The numbers in this table are tested using the methodology presented in
Table 77
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the
data Output. When this is true, add the appropriate Output adjustment from
For minimum delays use the values reported by the Timing Analyzer.
R
and
Table
When reading from the Output Flip-Flop
(OFF), the time from the active transition
at the OCLK input to data appearing at
the Output pin
The time it takes for data to travel from
the IOB’s O input to the Output pin
The time it takes for data to travel from
the O input through the OFF latch to the
Output pin
Time from asserting the OFF’s SR input
to setting/resetting data at the Output
pin
Time from asserting the Global Set
Reset (GSR) input on the
STARTUP_SPARTAN3E primitive to
setting/resetting data at the Output pin
80.
Description
www.xilinx.com
LVCMOS25
output drive, Fast slew
rate
LVCMOS25
output drive, Fast slew
rate
LVCMOS25
output drive, Fast slew
rate
Conditions
Table 95
Table
(2)
(2)
(2)
94.
, 12 mA
, 12 mA
, 12 mA
and are based on the operating conditions set forth in
DC and Switching Characteristics
Device
All
All
All
Speed Grade
Max
2.18
2.24
2.32
3.27
8.40
-5
Max
2.50
2.58
2.67
3.76
9.65
-4
Units
ns
ns
ns
ns
ns
131