XC3S1600E-4FGG484I Xilinx Inc, XC3S1600E-4FGG484I Datasheet - Page 63
![FPGA Spartan®-3E Family 1.6M Gates 33192 Cells 572MHz 90nm (CMOS) Technology 1.2V 484-Pin FBGA](/photos/6/72/67299/pk081-484_sml.jpg)
XC3S1600E-4FGG484I
Manufacturer Part Number
XC3S1600E-4FGG484I
Description
FPGA Spartan®-3E Family 1.6M Gates 33192 Cells 572MHz 90nm (CMOS) Technology 1.2V 484-Pin FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S1600E-4FGG484I
Package
484FBGA
Family Name
Spartan®-3E
Device Logic Cells
33192
Device Logic Units
3688
Device System Gates
1600000
Number Of Registers
29504
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
376
Ram Bits
663552
Number Of Logic Elements/cells
33192
Number Of Labs/clbs
3688
Total Ram Bits
663552
Number Of I /o
376
Number Of Gates
1600000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-XA3S1600E-UNI-G - KIT DEVELOPMENT AUTOMOTIVE ECU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S1600E-4FGG484I
Manufacturer:
XILINX
Quantity:
140
Company:
Part Number:
XC3S1600E-4FGG484I
Manufacturer:
XILINX
Quantity:
250
Company:
Part Number:
XC3S1600E-4FGG484I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S1600E-4FGG484I
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
The outputs of the top or bottom BUFGMUX elements con-
nect to two vertical spines, each comprising four vertical
clock lines as shown in
these clock signals connect to the eight-line horizontal clock
spine.
Outputs of the left and right BUFGMUX elements are routed
onto the left or right horizontal spines, each comprising
eight horizontal clock lines.
Each of the eight clock signals in a clock quadrant derives
either from a global clock signal or a half clock signal. In
other words, there are up to 24 total potential clock inputs to
the FPGA, eight of which can connect to clocked elements
DS312-2 (v3.8) August 26, 2009
Product Specification
R
Figure 47: Clock Sources for the Eight Clock Lines within a Clock Quadrant
a. Left (TL and BL Quadrants) Half of Die
BUFGMUX Output
X0Y9 (Left Half)
X0Y8 (Left Half)
X0Y7 (Left Half)
X0Y6 (Left Half)
X0Y5 (Left Half)
X0Y4 (Left Half)
X0Y3 (Left Half)
X0Y2 (Left Half)
X1Y10 (Global)
X1Y11 (Global)
X2Y10 (Global)
X2Y11 (Global)
X1Y0 (Global)
X1Y1 (Global)
X2Y0 (Global)
X2Y1 (Global)
Figure
45. At the center of the die,
Clock Line
H
G
F
E
D
C
B
A
www.xilinx.com
b. Right (TR and BR Quadrants) Half of Die
X3Y9 (Right Half)
X3Y8 (Right Half)
X3Y7 (Right Half)
X3Y6 (Right Half)
X3Y5 (Right Half)
X3Y4 (Right Half)
X3Y3 (Right Half)
X3Y2 (Right Half)
BUFGMUX Output
in a single clock quadrant.
lines in each quadrant are selected from associated BUFG-
MUX sources. For example, if quadrant clock ‘A’ in the bot-
tom left (BL) quadrant originates from BUFGMUX_X2Y1,
then the clock signal from BUFGMUX_X0Y2 is unavailable
in the bottom left quadrant. However, the top left (TL) quad-
rant clock ‘A’ can still solely use the output from either
BUFGMUX_X2Y1 or BUFGMUX_X0Y2 as the source.
To minimize the dynamic power dissipation of the clock net-
work, the Xilinx development software automatically dis-
ables all clock segments not in use.
X1Y10 (Global)
X1Y11 (Global)
X2Y10 (Global)
X2Y11 (Global)
X1Y0 (Global)
X1Y1 (Global)
X2Y0 (Global)
X2Y1 (Global)
DS312-2_17_103105
Figure 47
Clock Line
H
G
F
E
D
C
B
A
Functional Description
shows how the clock
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