XC3S1600E-5FGG400C Xilinx Inc, XC3S1600E-5FGG400C Datasheet - Page 33
![FPGA Spartan®-3E Family 1.6M Gates 33192 Cells 657MHz 90nm (CMOS) Technology 1.2V 400-Pin FBGA](/photos/6/72/67298/pk083-400_sml.jpg)
XC3S1600E-5FGG400C
Manufacturer Part Number
XC3S1600E-5FGG400C
Description
FPGA Spartan®-3E Family 1.6M Gates 33192 Cells 657MHz 90nm (CMOS) Technology 1.2V 400-Pin FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S1600E-5FGG400C
Package
400FBGA
Family Name
Spartan®-3E
Device Logic Cells
33192
Device Logic Units
3688
Device System Gates
1600000
Number Of Registers
29504
Maximum Internal Frequency
657 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
304
Ram Bits
663552
Number Of Logic Elements/cells
33192
Number Of Labs/clbs
3688
Total Ram Bits
663552
Number Of I /o
304
Number Of Gates
1600000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
400-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-XA3S1600E-UNI-G - KIT DEVELOPMENT AUTOMOTIVE ECU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Table 18: Dual-Port RAM Function
DS312-2 (v3.8) August 26, 2009
Product Specification
Notes:
1.
2.
WE (mode)
1 (write)
0 (read)
1 (read)
1 (read)
1 (read)
data_a = word addressed by bits A3-A0.
data_d = word addressed by bits DPRA3-DPRA0.
Figure 27: Dual-Port RAM Component
R
Inputs
WCLK
DPRA0
DPRA1
DPRA2
DPRA3
WCLK
↑
X
0
1
↓
WE
A0
A1
A2
A3
D
DPRA[3:0]
RAM16X1D
WCLK
A[3:0]
D
X
X
X
D
X
WE
D
DS312-2_42_021305
SPO
DPO
data_a
data_a
data_a
data_a
SPO
D
Figure 26: RAM16X1D Dual-Port Usage
Outputs
data_d
data_d
data_d
data_d
data_d
DPO
www.xilinx.com
(Read/
Write)
RAM
(Read
16x1
RAM
16x1
Only)
LUT
LUT
Table 19: Distributed RAM Signals
WCLK
WE
A0, A1, A2,
A3 (A4, A5)
D
O, SPO, and
DPO
SLICEM
Signal
Optional
Register
Optional
Register
The clock is used for synchronous writes.
The data and the address input pins have
setup times referenced to the WCLK pin.
Active on the positive edge by default
with built-in programmable polarity.
The enable pin affects the write
functionality of the port. An inactive Write
Enable prevents any writing to memory
cells. An active Write Enable causes the
clock edge to write the data input signal
to the memory location pointed to by the
address inputs. Active High by default
with built-in programmable polarity.
The address inputs select the memory
cells for read or write. The width of the
port determines the required address
inputs.
The data input provides the new data
value to be written into the RAM.
The data output O on single-port RAM or
the SPO and DPO outputs on dual-port
RAM reflects the contents of the memory
cells referenced by the address inputs.
Following an active write clock edge, the
data out (O or SPO) reflects the newly
written data.
DS312-2_41_021305
SPO
DPO
Description
Functional Description
33
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