XC3S1600E-5FGG400C Xilinx Inc, XC3S1600E-5FGG400C Datasheet - Page 9
![FPGA Spartan®-3E Family 1.6M Gates 33192 Cells 657MHz 90nm (CMOS) Technology 1.2V 400-Pin FBGA](/photos/6/72/67298/pk083-400_sml.jpg)
XC3S1600E-5FGG400C
Manufacturer Part Number
XC3S1600E-5FGG400C
Description
FPGA Spartan®-3E Family 1.6M Gates 33192 Cells 657MHz 90nm (CMOS) Technology 1.2V 400-Pin FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S1600E-5FGG400C
Package
400FBGA
Family Name
Spartan®-3E
Device Logic Cells
33192
Device Logic Units
3688
Device System Gates
1600000
Number Of Registers
29504
Maximum Internal Frequency
657 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
304
Ram Bits
663552
Number Of Logic Elements/cells
33192
Number Of Labs/clbs
3688
Total Ram Bits
663552
Number Of I /o
304
Number Of Gates
1600000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
400-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-XA3S1600E-UNI-G - KIT DEVELOPMENT AUTOMOTIVE ECU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number:
XC3S1600E-5FGG400C
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Quantity:
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Part Number:
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DS312-2 (v3.8) August 26, 2009
Design Documentation Available
The functionality of the Spartan®-3E FPGA family is now
described and updated in the following documents. The
topics covered in each guide are listed below.
•
© 2005–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other coun-
tries. All other trademarks are the property of their respective owners.
DS312-2 (v3.8) August 26, 2009
Product Specification
UG331: Spartan-3 Generation FPGA User Guide
http://www.xilinx.com/support/documentation/
user_guides/ug331.pdf
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Clocking Resources
Digital Clock Managers (DCMs)
Block RAM
Configurable Logic Blocks (CLBs)
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I/O Resources
Embedded Multiplier Blocks
Programmable Interconnect
ISE® Design Tools
IP Cores
Embedded Processing and Control Solutions
Pin Types and Package Overview
Package Drawings
Powering FPGAs
Power Management
Distributed RAM
SRL16 Shift Registers
Carry and Arithmetic Logic
R
116
www.xilinx.com
0
Spartan-3E FPGA Family:
Functional Description
Product Specification
•
For specific hardware examples, please see the Spartan-3E
Starter Kit board web page, which has links to various
design examples and the user guide.
•
•
Create a Xilinx MySupport user account and sign up to
receive automatic E-mail notification whenever this data
sheet or the associated user guides are updated.
•
UG332: Spartan-3 Generation Configuration User
Guide
http://www.xilinx.com/support/documentation/
user_guides/ug332.pdf
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Spartan-3E Starter Kit Board Page
http://www.xilinx.com/s3estarter
UG230: Spartan-3E Starter Kit User Guide
http://www.xilinx.com/support/documentation/
userguides/ug230.pdf
Sign Up for Alerts on Xilinx MySupport
http://www.xilinx.com/support/answers/19380.htm
Configuration Overview
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Detailed Descriptions by Mode
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ISE iMPACT Programming Examples
MultiBoot Reconfiguration
Configuration Pins and Behavior
Bitstream Sizes
Master Serial Mode using Xilinx® Platform Flash
PROM
Master SPI Mode using Commodity SPI Serial Flash
PROM
Master BPI Mode using Commodity Parallel NOR
Flash PROM
Slave Parallel (SelectMAP) using a Processor
Slave Serial using a Processor
JTAG Mode
9
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