XC3S250E-4FT256I Xilinx Inc, XC3S250E-4FT256I Datasheet - Page 154

• Manufacturer Part Number: XC3S250E-4FT256I
• Description: FPGA Spartan®-3E Family 250K Gates 5508 Cells 572MHz 90nm (CMOS) Technology 1.2V 256-Pin FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S250E-4FT256I

• Package: 256FTBGA
• Family Name: Spartan®-3E
• Device Logic Cells: 5508
• Device Logic Units: 612
• Device System Gates: 250000
• Number Of Registers: 4896
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 172
• Ram Bits: 221184
• Number Of Logic Elements/cells: 5508
• Number Of Labs/clbs: 612
• Total Ram Bits: 221184
• Number Of I /o: 172
• Number Of Gates: 250000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DC and Switching Characteristics
Slave Parallel Mode Timing
Table 117: Timing for the Slave Parallel Configuration Mode
154
(Open-Drain)
Notes:
1.
Clock-to-Output Times
T
Setup Times
T
T
T
SMCKBY
SMDCC
SMCSCC
SMCCW
RDWR_B
PROG_B
Symbol
(Output)
D0 - D7
(Inputs)
It is possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent
cycle for which CSI_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0 - D7 bus. When RDWR_B
switches High, be careful to avoid contention on the D0 - D7 bus.
INIT_B
(Input)
CSI_B
(Input)
(Input)
(Input)
CCLK
BUSY
(2)
The time from the rising transition on the CCLK pin to a signal transition at the
BUSY pin
The time from the setup of data at the D0-D7 pins to the active edge the CCLK
pin
Setup time on the CSI_B pin before the active edge of the CCLK pin
Setup time on the RDWR_B pin before active edge of the CCLK pin
High-Z
Figure 76: Waveforms for Slave Parallel Configuration
T
SMCCW
T
SMDCC
Description
Byte 0
T
SMCSCC
www.xilinx.com
T
SMCCD
Byte 1
T
SMCKBY
T
T
SCCH
MCCH
BUSY
1/F
Byte n
CCPAR
DS312-3 (v3.8) August 26, 2009
T
All Speed Grades
SMCKBY
11.0
10.0
23.0
Min
-
T
T
T
MCCL
SCCL
SMCCCS
Product Specification
Byte n+1
Max
12.0
-
-
-
DS312-3_02_103105
T
SMWCC
Units
High-Z
ns
ns
ns
ns
R