XC3S250E-4FT256I Xilinx Inc, XC3S250E-4FT256I Datasheet - Page 40

• Manufacturer Part Number: XC3S250E-4FT256I
• Description: FPGA Spartan®-3E Family 250K Gates 5508 Cells 572MHz 90nm (CMOS) Technology 1.2V 256-Pin FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S250E-4FT256I

• Package: 256FTBGA
• Family Name: Spartan®-3E
• Device Logic Cells: 5508
• Device Logic Units: 612
• Device System Gates: 250000
• Number Of Registers: 4896
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 172
• Ram Bits: 221184
• Number Of Logic Elements/cells: 5508
• Number Of Labs/clbs: 612
• Total Ram Bits: 221184
• Number Of I /o: 172
• Number Of Gates: 250000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Functional Description
Block RAM Attribute Definitions
A block RAM has a number of attributes that control its
behavior as shown in
Table 24: Block RAM Attributes
Block RAM Data Operations
Writing data to and accessing data from the block RAM are
synchronous operations that take place independently on
each of the two ports.
tions of each port as a result of the block RAM control sig-
nals in their default active-High edges.
Table 25: Block RAM Function Table
40
Initial Content for Data Memory, Loaded
during Configuration
Initial Content for Parity Memory, Loaded
during Configuration
Data Output Latch Initialization
Data Output Latch Synchronous
Set/Reset Value
Data Output Latch Behavior during Write
(see
GSR
1
0
0
0
0
Block RAM Data
EN
X
0
1
1
1
Loaded During Configuration
SSR
Function
X
X
1
1
0
Table
Table 25
Input Signals
WE
Operations)
X
X
0
1
0
24.
CLK
↑
↑
↑
X
X
describes the data opera-
Global Set/Reset Immediately After Configuration
ADDR
Synchronous Set/Reset During Write RAM
addr
addr
X
X
X
(INITP_00 through INITP0F)
Immediately After Configuration
Read RAM, no Write Operation
INITA, INITB (dual-port)
(INIT_00 through INIT3F)
pdata
SRVAL_A, SRVAL_B
DIP
SRVAL (single-port)
Synchronous Set/Reset
INIT (single-port)
X
X
X
X
WRITE_MODE
(dual-port)
Attribute
INITPxx
RAM Disabled
www.xilinx.com
INITxx
Data
DI
X
X
X
X
RAM(pdata)
The waveforms for the write operation are shown in the top
half of
and EN signals enable the active edge of CLK, data at the
DI input bus is written to the block RAM location addressed
by the ADDR lines.
No Chg
SRVAL
SRVAL
DOP
INIT
X
Output Signals
Figure
Each initialization string defines 32 hex values of
the 16384-bit data memory of the block RAM.
Each initialization string defines 32 hex values of
the 2048-bit parity data memory of the block
RAM.
Hex value the width of the chosen port.
Hex value the width of the chosen port.
WRITE_FIRST, READ_FIRST, NO_CHANGE
33,
RAM(data)
No Chg
SRVAL
SRVAL
Figure
INIT
DO
X
34, and
Possible Values
DS312-2 (v3.8) August 26, 2009
RAM(addr)
INITP_xx
← pdata
No Chg
No Chg
No Chg
No Chg
Parity
Figure
RAM Data
Product Specification
35. When the WE
RAM(addr)
INIT_xx
No Chg
No Chg
No Chg
No Chg
← data
Data
R