XC3S250E-4FT256I Xilinx Inc, XC3S250E-4FT256I Datasheet - Page 50

• Manufacturer Part Number: XC3S250E-4FT256I
• Description: FPGA Spartan®-3E Family 250K Gates 5508 Cells 572MHz 90nm (CMOS) Technology 1.2V 256-Pin FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S250E-4FT256I

• Package: 256FTBGA
• Family Name: Spartan®-3E
• Device Logic Cells: 5508
• Device Logic Units: 612
• Device System Gates: 250000
• Number Of Registers: 4896
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 172
• Ram Bits: 221184
• Number Of Logic Elements/cells: 5508
• Number Of Labs/clbs: 612
• Total Ram Bits: 221184
• Number Of I /o: 172
• Number Of Gates: 250000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Functional Description
clock distribution network, the clock signal returns to the
DLL via a feedback line called CLKFB. The control block
inside the DLL measures the phase error between CLKFB
and CLKIN. This phase error is a measure of the clock skew
that the clock distribution network introduces. The control
block activates the appropriate number of delay steps to
cancel out the clock skew. When the DLL phase-aligns the
Table 29: DLL Attributes
DLL Clock Input Connections
For best results, an external clock source enters the FPGA
via a Global Clock Input (GCLK). Each specific DCM has
four possible direct, optimal GCLK inputs that feed the
DCM’s CLKIN input, as shown in
provides the specific pin numbers by package for each
GCLK input. The two additional DCM’s on the XC3S1200E
and XC3S1600E have similar optimal connections from the
left-edge LHCLK and the right-edge RHCLK inputs, as
described in
50
CLK_FEEDBACK
CLKIN_DIVIDE_BY_2
CLKDV_DIVIDE
CLKIN_PERIOD
Attribute
Table 31
and
Table
32.
Table
Chooses either the CLK0 or CLK2X output to
drive the CLKFB input
Halves the frequency of the CLKIN signal just
as it enters the DCM
Selects the constant used to divide the CLKIN
input frequency to generate the CLKDV
output frequency
Additional information that allows the DLL to
operate with the most efficient lock time and
the best jitter tolerance
30.
Table 30
Description
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also
CLK0 signal with the CLKIN signal, it asserts the LOCKED
output, indicating a lock on to the CLKIN signal.
DLL Attributes and Related Functions
The DLL unit has a variety of associated attributes as
described in
the sections that follow.
•
Design Note
Avoid using global clock input GCLK1 as it is always shared
with the M2 mode select pin. Global clock inputs GCLK0,
GCLK2, GCLK3, GCLK12, GCLK13, GCLK14, and
GCLK15 have shared functionality in some configuration
The DCM supports differential clock inputs (for
example, LVDS, LVPECL_25) via a pair of GCLK inputs
that feed an internal single-ended signal to the DCM’s
CLKIN input.
Table
29. Each attribute is described in detail in
NONE, 1X, 2X
FALSE, TRUE
1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6.0,
6.5, 7.0, 7.5, 8, 9, 10, 11, 12, 13, 14,
15, and 16
Floating-point value representing the
CLKIN period in nanoseconds
DS312-2 (v3.8) August 26, 2009
Values
Product Specification
R