XC3S250E-4PQG208C Xilinx Inc, XC3S250E-4PQG208C Datasheet - Page 118

• Manufacturer Part Number: XC3S250E-4PQG208C
• Description: FPGA Spartan®-3E Family 250K Gates 5508 Cells 572MHz 90nm (CMOS) Technology 1.2V 208-Pin PQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S250E-4PQG208C

• Package: 208PQFP
• Family Name: Spartan®-3E
• Device Logic Cells: 5508
• Device Logic Units: 612
• Device System Gates: 250000
• Number Of Registers: 4896
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 158
• Ram Bits: 221184
• Number Of Logic Elements/cells: 5508
• Number Of Labs/clbs: 612
• Total Ram Bits: 221184
• Number Of I /o: 158
• Number Of Gates: 250000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1483

DC and Switching Characteristics
Power Supply Specifications
Table 74: Supply Voltage Thresholds for Power-On Reset
Table 75: Supply Voltage Ramp Rate
Table 76: Supply Voltage Levels Necessary for Preserving RAM Contents
118
Notes:
1.
2.
Notes:
1.
2.
Notes:
1.
V
SPI Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration
source. In Step 0 devices using the HSWAP internal pull-up, V
To ensure successful power-on, V
no dips at any point.
V
SPI Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration
source. In Step 0 devices using the HSWAP internal pull-up, V
To ensure successful power-on, V
no dips at any point.
Symbol
RAM contents include configuration data.
V
V
CCINT
CCINT
DRAUX
V
V
DRINT
V
Symbol
V
Symbol
V
V
CCAUXR
CCAUXT
CCINTR
CCINTT
CCO2R
CCO2T
, V
, V
CCAUX
CCAUX
, and V
, and V
V
V
CCINT
CCAUX
Threshold for the V
Threshold for the V
Threshold for the V
Ramp rate from GND to valid V
Ramp rate from GND to valid V
Ramp rate from GND to valid V
CCO
CCO
level required to retain RAM data
level required to retain RAM data
supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (Platform Flash,
supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (Platform Flash,
CCINT
CCINT
, V
, V
CCO
CCO
CCINT
CCAUX
CCO
Bank 2, and V
Bank 2, and V
Description
Description
Bank 2 supply
supply
supply
Description
www.xilinx.com
CCINT
CCAUX
CCO
CCAUX
CCAUX
CCINT
CCINT
Bank 2 supply level
supply level
supplies must rise through their respective threshold-voltage ranges with
supplies must rise through their respective threshold-voltage ranges with
supply level
must be applied before V
must be applied before V
CCAUX
CCAUX
Min
Min
0.4
0.8
0.4
0.2
0.2
0.2
.
.
DS312-3 (v3.8) August 26, 2009
Max
Max
1.0
2.0
1.0
50
50
50
Product Specification
Min
1.0
2.0
Units
Units
Units
ms
ms
ms
V
V
V
V
V
R