XC3S250E-4PQG208I Xilinx Inc, XC3S250E-4PQG208I Datasheet - Page 144
![FPGA Spartan®-3E Family 250K Gates 5508 Cells 572MHz 90nm (CMOS) Technology 1.2V 208-Pin PQFP](/photos/6/71/67100/pq208_sml.jpg)
XC3S250E-4PQG208I
Manufacturer Part Number
XC3S250E-4PQG208I
Description
FPGA Spartan®-3E Family 250K Gates 5508 Cells 572MHz 90nm (CMOS) Technology 1.2V 208-Pin PQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S250E-4PQG208I
Package
208PQFP
Family Name
Spartan®-3E
Device Logic Cells
5508
Device Logic Units
612
Device System Gates
250000
Number Of Registers
4896
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
158
Ram Bits
221184
Number Of Logic Elements/cells
5508
Number Of Labs/clbs
612
Total Ram Bits
221184
Number Of I /o
158
Number Of Gates
250000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
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XILINX
Quantity:
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Part Number:
XC3S250E-4PQG208I
Manufacturer:
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Quantity:
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Company:
Part Number:
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Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S250E-4PQG208I
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
DC and Switching Characteristics
Table 105: Switching Characteristics for the DLL
144
Output Frequency Ranges
CLKOUT_FREQ_CLK0
CLKOUT_FREQ_CLK90
CLKOUT_FREQ_2X
CLKOUT_FREQ_DV
Output Clock Jitter
CLKOUT_PER_JITT_0
CLKOUT_PER_JITT_90
CLKOUT_PER_JITT_180
CLKOUT_PER_JITT_270
CLKOUT_PER_JITT_2X
CLKOUT_PER_JITT_DV1
CLKOUT_PER_JITT_DV2
Duty Cycle
CLKOUT_DUTY_CYCLE_DLL Duty cycle variation for the CLK0, CLK90, CLK180,
Symbol
(4)
(2,3,4)
Frequency for the CLK0 and
CLK180 outputs
Frequency for the CLK90 and
CLK270 outputs
Frequency for the CLK2X and
CLK2X180 outputs
Frequency for the CLKDV output
Period jitter at the CLK0 output
Period jitter at the CLK90 output
Period jitter at the CLK180 output
Period jitter at the CLK270 output
Period jitter at the CLK2X and CLK2X180 outputs
Period jitter at the CLKDV output when performing
integer division
Period jitter at the CLKDV output when performing
non-integer division
CLK270, CLK2X, CLK2X180, and CLKDV outputs,
including the BUFGMUX and clock tree duty-cycle
distortion
Description
www.xilinx.com
Stepping 0
Stepping 1
Stepping 0
Stepping 1
Stepping 0
Stepping 1
Stepping 0
Stepping 1
XC3S1600E
XC3S1200E
XC3S1600E
XC3S1200E
XC3S1600E
XC3S1200E
XC3S1600E
XC3S1200E
XC3S100E
XC3S250E
XC3S500E
XC3S100E
XC3S250E
XC3S500E
XC3S100E
XC3S250E
XC3S500E
XC3S100E
XC3S250E
XC3S500E
Device
All
All
All
All
All
All
0.3125
Min
N/A
N/A
N/A
N/A
10
5
5
-
-
-
-
-
-
-
-
-5
DS312-3 (v3.8) August 26, 2009
±[1% of
±[1% of
±[1% of
CLKIN
CLKIN
CLKIN
period
+ 150]
period
+ 200]
period
+ 400]
±100
±150
±150
±150
±150
Max
Speed Grade
N/A
275
N/A
200
N/A
333
N/A
183
0.3125
Product Specification
Min
10
5
5
-
-
-
-
-
-
-
-
-4
±[1% of
±[1% of
±[1% of
CLKIN
period
+ 150]
CLKIN
period
+ 200]
CLKIN
period
+ 400]
±100
±150
±150
±150
±150
Max
200
240
167
200
180
311
311
133
160
90
90
60
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
ps
R