XC3S250E-4PQG208I Xilinx Inc, XC3S250E-4PQG208I Datasheet - Page 153
![FPGA Spartan®-3E Family 250K Gates 5508 Cells 572MHz 90nm (CMOS) Technology 1.2V 208-Pin PQFP](/photos/6/71/67100/pq208_sml.jpg)
XC3S250E-4PQG208I
Manufacturer Part Number
XC3S250E-4PQG208I
Description
FPGA Spartan®-3E Family 250K Gates 5508 Cells 572MHz 90nm (CMOS) Technology 1.2V 208-Pin PQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S250E-4PQG208I
Package
208PQFP
Family Name
Spartan®-3E
Device Logic Cells
5508
Device Logic Units
612
Device System Gates
250000
Number Of Registers
4896
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
158
Ram Bits
221184
Number Of Logic Elements/cells
5508
Number Of Labs/clbs
612
Total Ram Bits
221184
Number Of I /o
158
Number Of Gates
250000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Master Serial and Slave Serial Mode Timing
Table 116: Timing for the Master Serial and Slave Serial Configuration Modes
DS312-3 (v3.8) August 26, 2009
Product Specification
(Input/Output)
Notes:
1.
2.
(Open-Drain)
Clock-to-Output Times
T
Setup Times
T
Hold Times
T
Clock Timing
T
T
F
Symbol
CCO
DCC
CCD
CCH
CCL
CCSER
PROG_B
The numbers in this table are based on the operating conditions set forth in
For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
(Output)
INIT_B
(Input)
(Input)
DOUT
CCLK
DIN
R
The time from the falling transition on the CCLK pin to data
appearing at the DOUT pin
The time from the setup of data at the DIN pin to the active edge of
the CCLK pin
The time from the active edge of the CCLK pin to the point when
data is last held at the DIN pin
High pulse width at the CCLK input pin
Low pulse width at the CCLK input pin
Frequency of the clock signal at
the CCLK input pin
Figure 75: Waveforms for Master Serial and Slave Serial Configuration
Description
T
DCC
Bit 0
No bitstream compression
With bitstream compression
www.xilinx.com
T
CCD
Bit 1
Table
77.
T
T
Master
Master
Master
Slave/
MCCL
Slave
Slave
Slave
SCCL
Both
Both
Both
DC and Switching Characteristics
Bit n
1/F
CCSER
T
CCO
Bit n-64
All Speed Grades
Bit n+1
11.0
Min
1.5
T
T
0
0
0
MCCH
SCCH
See
See
See
See
Bit n-63
Table 114
Table 115
Table 114
Table 115
66
Max
10.0
20
-
-
(2)
DS312-3_05_103105
Units
MHz
MHz
ns
ns
ns
153