XC3S250E-4PQG208I Xilinx Inc, XC3S250E-4PQG208I Datasheet - Page 155

FPGA Spartan®-3E Family 250K Gates 5508 Cells 572MHz 90nm (CMOS) Technology 1.2V 208-Pin PQFP

XC3S250E-4PQG208I

Manufacturer Part Number
XC3S250E-4PQG208I
Description
FPGA Spartan®-3E Family 250K Gates 5508 Cells 572MHz 90nm (CMOS) Technology 1.2V 208-Pin PQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet

Specifications of XC3S250E-4PQG208I

Package
208PQFP
Family Name
Spartan®-3E
Device Logic Cells
5508
Device Logic Units
612
Device System Gates
250000
Number Of Registers
4896
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
158
Ram Bits
221184
Number Of Logic Elements/cells
5508
Number Of Labs/clbs
612
Total Ram Bits
221184
Number Of I /o
158
Number Of Gates
250000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Table 117: Timing for the Slave Parallel Configuration Mode (Continued)
DS312-3 (v3.8) August 26, 2009
Product Specification
Notes:
1.
2.
3.
Hold Times
T
T
T
Clock Timing
T
T
F
SMCCD
SMCCCS
SMWCC
CCH
CCL
CCPAR
Symbol
The numbers in this table are based on the operating conditions set forth in
In the Slave Parallel mode, it is necessary to use the BUSY pin when the CCLK frequency exceeds this maximum specification.
Some Xilinx documents refer to Parallel modes as “SelectMAP” modes.
R
The time from the active edge of the CCLK pin to the point when data is last
held at the D0-D7 pins
The time from the active edge of the CCLK pin to the point when a logic level
is last held at the CSO_B pin
The time from the active edge of the CCLK pin to the point when a logic level
is last held at the RDWR_B pin
The High pulse width at the CCLK input pin
The Low pulse width at the CCLK input pin
Frequency of the clock
signal at the CCLK input
pin
No bitstream
compression
With bitstream compression
Description
www.xilinx.com
Not using the BUSY pin
Using the BUSY pin
Table
77.
DC and Switching Characteristics
(2)
All Speed Grades
Min
1.0
0
0
5
5
0
0
0
Max
50
66
20
-
-
-
-
-
Units
MHz
MHz
MHz
ns
ns
ns
ns
ns
155

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