XC3S250E-4PQG208I Xilinx Inc, XC3S250E-4PQG208I Datasheet - Page 44
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XC3S250E-4PQG208I
Manufacturer Part Number
XC3S250E-4PQG208I
Description
FPGA Spartan®-3E Family 250K Gates 5508 Cells 572MHz 90nm (CMOS) Technology 1.2V 208-Pin PQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S250E-4PQG208I
Package
208PQFP
Family Name
Spartan®-3E
Device Logic Cells
5508
Device Logic Units
612
Device System Gates
250000
Number Of Registers
4896
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
158
Ram Bits
221184
Number Of Logic Elements/cells
5508
Number Of Labs/clbs
612
Total Ram Bits
221184
Number Of I /o
158
Number Of Gates
250000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
208-BFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Functional Description
Dedicated Multipliers
For additional information, refer to the “Using Embedded
Multipliers” chapter in UG331.
The Spartan-3E devices provide 4 to 36 dedicated multiplier
blocks per device. The multipliers are located together with
the block RAM in one or two columns depending on device
density. See
details on the location of these blocks and their connectivity.
Operation
The multiplier blocks primarily perform two’s complement
numerical multiplication but can also perform some less
obvious applications, such as simple data storage and bar-
rel shifting. Logic slices also implement efficient small multi-
pliers and thereby supplement the dedicated multipliers.
The Spartan-3E dedicated multiplier blocks have additional
features beyond those provided in Spartan-3 FPGAs.
Each multiplier performs the principle operation P = A × B,
where ‘A’ and ‘B’ are 18-bit words in two’s complement
form, and ‘P’ is the full-precision 36-bit product, also in two’s
complement form. The 18-bit inputs represent values rang-
ing from -131,072
ranging from -17,179,738,112
Use the MULT18X18SIO primitive shown in
instantiate a multiplier within a design. Although high-level
logic synthesis software usually automatically infers a multi-
plier, adding the pipeline registers might require the
MULT18X18SIO primitive. Connect the appropriate signals
44
Arrangement of RAM Blocks on Die
10
to +131,071
Figure 36: Principle Ports and Functions of Dedicated Multiplier Blocks
A[17:0]
B[17:0]
RSTB
RSTA
CEA
CEB
CLK
10
to +17,179,869,184
10
with a resulting product
CE
D
CE
D
(Optional)
(Optional)
AREG
BREG
RST
RST
Figure 37
Q
Q
10
www.xilinx.com
.
for
to
X
Implement multipliers with inputs less than 18 bits by
sign-extending the inputs (i.e., replicating the most-signifi-
cant bit). Wider multiplication operations are performed by
combining the dedicated multipliers and slice-based logic in
any viable combination or by time-sharing a single multi-
plier. Perform unsigned multiplication by restricting the
inputs to the positive range. Tie the most-significant bit Low
and represent the unsigned value in the remaining 17
lesser-significant bits.
Optional Pipeline Registers
As shown in
registers on each of the multiplier inputs and the output. The
registers are named AREG, BREG, and PREG and can be
used in any combination. The clock input is common to all
the registers within a block, but each register has an inde-
pendent clock enable and synchronous reset controls mak-
ing them ideal for storing data samples and coefficients.
When used for pipelining, the registers boost the multiplier
clock rate, beneficial for higher performance applications.
Figure 36
block.
to the MULT18X18SIO multiplier ports and set the individual
AREG, BREG, and PREG attributes to ‘1’ to insert the asso-
ciated register, or to 0 to remove it and make the signal path
combinatorial.
RSTP
CEP
illustrates the principle features of the multiplier
CE
D
Figure
(Optional)
PREG
RST
Q
36, each multiplier block has optional
DS312-2_27_021205
P[35:0]
DS312-2 (v3.8) August 26, 2009
Product Specification
R