XC3S50-4VQG100C Xilinx Inc, XC3S50-4VQG100C Datasheet - Page 211
![FPGA Spartan®-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 100-Pin VTQFP](/photos/6/70/67082/100-tqfp_sml.jpg)
XC3S50-4VQG100C
Manufacturer Part Number
XC3S50-4VQG100C
Description
FPGA Spartan®-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 100-Pin VTQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3r
Datasheet
1.XC3S50-4VQG100C.pdf
(217 pages)
Specifications of XC3S50-4VQG100C
Package
100VTQFP
Family Name
Spartan®-3
Device Logic Units
1728
Device System Gates
50000
Maximum Internal Frequency
630 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
63
Ram Bits
73728
Number Of Logic Elements/cells
1728
Number Of Labs/clbs
192
Total Ram Bits
73728
Number Of I /o
63
Number Of Gates
50000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
100-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1504
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S50-4VQG100C
Manufacturer:
LT
Quantity:
714
Company:
Part Number:
XC3S50-4VQG100C
Manufacturer:
Xilinx Inc
Quantity:
1 869
Part Number:
XC3S50-4VQG100C
Manufacturer:
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Quantity:
20 000
Table 109: FG1156 Package Pinout (Continued)
Table 110: User I/Os Per Bank for XC3S4000 in FG1156 Package
Table 111: User I/Os Per Bank for XC3S5000 in FG1156 Package
DS099-4 (v2.5) December 4, 2009
Product Specification
VCCAUX HSWAP_EN
VCCAUX M0
VCCAUX M1
VCCAUX M2
VCCAUX PROG_B
VCCAUX TCK
VCCAUX TDI
VCCAUX TDO
VCCAUX TMS
Package Edge
Package Edge
Bank
Bottom
Bottom
Right
Right
Left
Left
Top
Top
R
XC3S4000
Pin Name
Bank
Bank
I/O
I/O
HSWAP_EN
M0
M1
M2
PROG_B
TCK
TDI
TDO
TMS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
XC3S5000
Pin Name
Maximum
Maximum
100
100
100
100
I/O
I/O
90
90
88
88
90
90
88
88
96
96
96
96
Number
FG1156
AG8
AK4
D31
H27
L11
AL4
E31
Pin
D4
E4
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
JTAG
JTAG
JTAG
JTAG
Type
I/O
I/O
79
79
80
79
73
73
79
79
89
89
87
87
83
83
87
87
www.xilinx.com
User I/Os by Bank
Table 110
tributed between the eight I/O banks for the XC3S4000 in
the FG1156 package. Similarly,
available user-I/O pins are distributed between the eight I/O
banks for the XC3S5000 in the FG1156 package.
DUAL
DUAL
Note: The FG(G)1156 package is being discontinued and is
not recommended for new designs. See
http://www.xilinx.com/support/documentation/
spartan-3_customer_notices.htm
0
0
0
0
6
6
0
0
0
0
0
0
6
6
0
0
All Possible I/O Pins by Type
All Possible I/O Pins by Type
indicates how the available user-I/O pins are dis-
Spartan-3 FPGA Family: Pinout Descriptions
DCI
DCI
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
VREF
VREF
Table 111
7
7
6
7
7
7
7
7
7
7
7
7
7
7
7
7
for the latest updates
shows how the
GCLK
GCLK
2
2
0
0
2
2
0
0
2
2
0
0
2
2
0
0
211