XC3S50-4VQG100C Xilinx Inc, XC3S50-4VQG100C Datasheet - Page 69
![FPGA Spartan®-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 100-Pin VTQFP](/photos/6/70/67082/100-tqfp_sml.jpg)
XC3S50-4VQG100C
Manufacturer Part Number
XC3S50-4VQG100C
Description
FPGA Spartan®-3 Family 50K Gates 1728 Cells 630MHz 90nm Technology 1.2V 100-Pin VTQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3r
Datasheet
1.XC3S50-4VQG100C.pdf
(217 pages)
Specifications of XC3S50-4VQG100C
Package
100VTQFP
Family Name
Spartan®-3
Device Logic Units
1728
Device System Gates
50000
Maximum Internal Frequency
630 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
63
Ram Bits
73728
Number Of Logic Elements/cells
1728
Number Of Labs/clbs
192
Total Ram Bits
73728
Number Of I /o
63
Number Of Gates
50000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
100-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1504
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S50-4VQG100C
Manufacturer:
LT
Quantity:
714
Company:
Part Number:
XC3S50-4VQG100C
Manufacturer:
Xilinx Inc
Quantity:
1 869
Part Number:
XC3S50-4VQG100C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Table 41: Setup and Hold Times for the IOB Input Path
DS099-3 (v2.5) December 4, 2009
Product Specification
98
Notes:
1.
2.
3.
Setup Times
Hold Times
Set/Reset Pulse Width
T
The numbers in this table are tested using the methodology presented in
Table 31
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from
These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from
edge.
T
T
Symbol
T
T
RPW_IOB
IOPICKD
IOICKPD
IOPICK
IOICKP
R
and
Table
Time from the setup of data at the Input
pin to the active transition at the ICLK
input of the Input Flip-Flop (IFF). No Input
Delay is programmed.
Time from the setup of data at the Input
pin to the active transition at the IFF’s
ICLK input. The Input Delay is
programmed.
Time from the active transition at the IFF’s
ICLK input to the point where data must
be held at the Input pin. No Input Delay is
programmed.
Time from the active transition at the IFF’s
ICLK input to the point where data must
be held at the Input pin. The Input Delay
is programmed.
Minimum pulse width to SR control input
on IOB
34.
Description
Table
Table
43.
43. When the hold time is negative, it is possible to change the data before the clock’s active
Spartan-3 FPGA Family: DC and Switching Characteristics
www.xilinx.com
LVCMOS25
IOBDELAY = NONE
LVCMOS25
IOBDELAY = IFD
LVCMOS25
IOBDELAY = NONE
LVCMOS25
IOBDELAY = IFD
Conditions
(2)
(2)
(2)
(2)
Table 47
,
,
,
,
and are based on the operating conditions set forth in
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
Device
All
-0.55
-0.29
-0.29
-0.55
-0.55
-0.55
-0.61
-0.68
-2.74
-3.00
-2.90
-3.24
-3.55
-4.57
-4.96
-5.09
1.65
1.37
1.37
1.65
1.65
1.65
1.73
1.82
4.39
4.76
4.63
5.02
5.40
6.68
7.16
7.33
0.66
Min
-5
Speed Grade
-0.55
-0.55
-0.55
-0.55
-0.61
-0.68
-2.74
-3.24
-3.55
-4.57
-4.96
-5.09
-0.29
-0.29
-3.00
-2.90
1.89
1.57
1.57
1.89
1.89
1.89
1.99
2.09
5.04
5.47
5.32
5.76
6.20
7.68
8.24
8.42
0.76
Min
-4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
69