XCV100E-6FG256I Xilinx Inc, XCV100E-6FG256I Datasheet - Page 42

• Manufacturer Part Number: XCV100E-6FG256I
• Description: FPGA Virtex™-E Family 32.4K Gates 2700 Cells 357MHz 0.18um (CMOS) Technology 1.8V 256-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV100E-6FG256I

• Package: 256FBGA
• Family Name: Virtex™-E
• Device Logic Gates: 32400
• Device Logic Units: 2700
• Device System Gates: 128236
• Maximum Internal Frequency: 357 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 176
• Ram Bits: 81920
• Number Of Logic Elements/cells: 2700
• Number Of Labs/clbs: 600
• Total Ram Bits: 81920
• Number Of I /o: 176
• Number Of Gates: 128236
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Field Programmable Gate Arrays
LVTTL 3-state output buffers have selectable drive
strengths.
The format for LVTTL OBUFT symbol names is as follows:
where <slew_rate> is either F (Fast) or S (Slow), and
<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,
or 24).
The following list details variations of the OBUFT symbol.
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Module 2 of 4
36
Figure 41: 3-State Output Buffer Symbol (OBUFT)
OBUFT_<slew_rate>_<drive_strength>
OBUFT
OBUFT_S_2
OBUFT_S_4
OBUFT_S_6
OBUFT_S_8
OBUFT_S_12
OBUFT_S_16
OBUFT_S_24
OBUFT_F_2
OBUFT_F_4
OBUFT_F_6
OBUFT_F_8
OBUFT_F_12
OBUFT_F_16
OBUFT_F_24
OBUFT_LVCMOS2
OBUFT_PCI33_3
OBUFT_PCI66_3
OBUFT_GTL
OBUFT_GTLP
OBUFT_HSTL_I
OBUFT_HSTL_III
OBUFT_HSTL_IV
OBUFT_SSTL3_I
OBUFT_SSTL3_II
OBUFT_SSTL2_I
OBUFT_SSTL2_II
OBUFT_CTT
OBUFT_AGP
OBUFT_LVCMOS18
OBUFT_LVDS
OBUFT_LVPECL
T
I
OBUFT
x133_05_111699
O
www.xilinx.com
The Virtex-E series supports eight banks for the HQ and PQ
packages. The CS package supports four V
The SelectI/O OBUFT placement restrictions require that
within a given V
put source drive voltage. Input buffers of any type and out-
put buffers that do not require V
the same V
The LOC property can specify a location for the OBUFT.
3-state output buffers and bidirectional buffers can have
either a weak pull-up resistor, a weak pull-down resistor, or
a weak “keeper” circuit. Control this feature by adding the
appropriate symbol to the output net of the OBUFT (PUL-
LUP, PULLDOWN, or KEEPER).
The weak “keeper” circuit requires the input buffer within the
IOB to sample the I/O signal. So, OBUFTs programmed for
an I/O standard that requires a V
ment of a V
a weak “keeper” circuit. This restriction does not affect most
circuit design as applications using an OBUFT configured
with a weak “keeper” typically implement a bidirectional I/O.
In this case the IBUF (and the corresponding V
explicitly placed.
The LOC property can specify a location for the OBUFT.
IOBUF
Use the IOBUF symbol for bidirectional signals that require
both an input buffer and a 3-state output buffer with an
active high 3-state pin. The generic input/output buffer
IOBUF appears in
The extension to the base name defines which I/O standard
the IOBUF uses. With no extension specified for the generic
IOBUF symbol, the assumed standard is LVTTL input buffer
and slew rate limited LVTTL with 12 mA drive strength for
the output buffer.
The LVTTL IOBUF additionally can support one of two slew
rate modes to minimize bus transients. By default, the slew
rate for each output buffer is reduced to minimize power bus
transients when switching non-critical signals.
LVTTL bidirectional buffers have selectable output drive
strengths.
The format for LVTTL IOBUF symbol names is as follows:
where <slew_rate> is either F (Fast) or S (Slow), and
<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,
or 24).
IOBUF_<slew_rate>_<drive_strength>
CCO
REF
CCO
in the bank with an OBUFT configured with
bank.
Figure
bank each OBUFT share the same out-
42.
Production Product Specification
DS022-2 (v2.8) January 16, 2006
REF
CCO
have automatic place-
can be placed within
CCO
banks.
REF
) are
R