XCV100E-6FG256I Xilinx Inc, XCV100E-6FG256I Datasheet - Page 98
![no-image](/images/no-image-200.jpg)
XCV100E-6FG256I
Manufacturer Part Number
XCV100E-6FG256I
Description
FPGA Virtex™-E Family 32.4K Gates 2700 Cells 357MHz 0.18um (CMOS) Technology 1.8V 256-Pin FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-Er
Specifications of XCV100E-6FG256I
Package
256FBGA
Family Name
VirtexÂ-E
Device Logic Gates
32400
Device Logic Units
2700
Device System Gates
128236
Maximum Internal Frequency
357 MHz
Typical Operating Supply Voltage
1.8 V
Maximum Number Of User I/os
176
Ram Bits
81920
Number Of Logic Elements/cells
2700
Number Of Labs/clbs
600
Total Ram Bits
81920
Number Of I /o
176
Number Of Gates
128236
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Virtex™-E 1.8 V Field Programmable Gate Arrays
Table 7: PQ240 Differential Pin Pair Summary
XCV50E, XCV100E, XCV200E, XCV300E, XCV400E
Module 4 of 4
12
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Pair
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
AO in the XCV50E.
AO in the XCV50E, 100E, 200E, 300E.
AO in the XCV50E, 200E, 300E, 400E.
AO in the XCV50E, 300E, 400E.
AO in the XCV100E, 200E, 400E.
AO in the XCV100E, 400E.
AO in the XCV50E, 200E, 400E.
AO in the XCV100E.
Bank
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
P Pin
P56
P52
P49
P46
P41
P38
P35
P33
P27
P23
P20
P17
P12
P9
P6
P4
N Pin
P57
P53
P50
P47
P42
P39
P36
P34
P28
P24
P21
P18
P13
P10
P7
P5
AO
2
2
2
3
2
6
√
3
4
√
4
5
√
4
√
4
Functions
Other
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
-
-
-
-
-
-
-
-
www.xilinx.com
1-800-255-7778
HQ240 High-Heat Quad Flat-Pack Packages
XCV600E and XCV1000E devices in High-heat dissipation
Quad Flat-pack packages have footprint compatibility. Pins
labeled I0_VREF can be used as either in all parts unless
device-dependent as indicated in the footnotes. If the pin is
not used as V
ately following
mation.
Table 8: HQ240 — XCV600E, XCV1000E
Pin #
P240
P239
P238
P237
P236
P235
P234
P233
P232
P231
P230
P229
P228
P227
P226
P225
P224
P223
P222
P221
P220
P219
P218
P217
P216
P215
P214
P213
P212
P211
REF
Table
, it can be used as general I/O. Immedi-
8, see
IO_LVDS_DLL_L6N
IO_VREF_L2N_YY
IO_VREF_L5N_Y
Pin Description
IO_VREF_L0P
IO_L1N_YY
IO_L3N_YY
IO_L1P_YY
IO_L2P_YY
IO_L3P_YY
IO_L4N_Y
IO_L4P_Y
IO_L5P_Y
Production Product Specification
Table 9
IO_VREF
IO_VREF
IO_VREF
IO_VREF
VCCINT
VCCINT
IO_L0N
VCCO
VCCO
VCCO
VCCO
GCK3
GND
GND
GND
GND
TCK
DS022-4 (v2.5) March 14, 2003
IO
for Differential Pair infor-
Bank
NA
NA
NA
NA
NA
NA
NA
0
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
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