XCV100E-6FG256I Xilinx Inc, XCV100E-6FG256I Datasheet - Page 77

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XCV100E-6FG256I

Manufacturer Part Number
XCV100E-6FG256I
Description
FPGA Virtex™-E Family 32.4K Gates 2700 Cells 357MHz 0.18um (CMOS) Technology 1.8V 256-Pin FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-Er
Datasheets

Specifications of XCV100E-6FG256I

Package
256FBGA
Family Name
Virtex™-E
Device Logic Gates
32400
Device Logic Units
2700
Device System Gates
128236
Maximum Internal Frequency
357 MHz
Typical Operating Supply Voltage
1.8 V
Maximum Number Of User I/os
176
Ram Bits
81920
Number Of Logic Elements/cells
2700
Number Of Labs/clbs
600
Total Ram Bits
81920
Number Of I /o
176
Number Of Gates
128236
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XCV100E-6FG256I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XCV100E-6FG256I
Manufacturer:
XILINX
0
Block RAM Switching Characteristics
TBUF Switching Characteristics
JTAG Test Access Port Switching Characteristics
DS022-3 (v2.9.2) March 14, 2003
Production Product Specification
Notes:
1.
Sequential Delays
Clock CLK to DOUT output
Setup and Hold Times before Clock CLK
ADDR inputs
DIN inputs
EN input
RST input
WEN input
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
CLKA -> CLKB setup time for different ports
Combinatorial Delays
IN input to OUT output
TRI input to OUT output high-impedance
TRI input to valid data on OUT output
TMS and TDI Setup times before TCK
TMS and TDI Hold times after TCK
Output delay from clock TCK to output TDO
Maximum TCK clock frequency
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
R
Description
Description
Description
T
T
T
T
T
BWCK
BDCK
BECK
BRCK
BACK
Symbol
T
T
T
T
www.xilinx.com
1-800-255-7778
BPWH
BPWL
BCKO
BCCS
/T
/T
/T
/T
/T
Symbol
BCKA
BCKD
BCKE
BCKR
BCKW
T
T
T
OFF
ON
IO
0.42 / 0
0.42 / 0
0.97 / 0
0.86 / 0
0.9 / 0
0.63
Min
0.6
0.6
1.2
Virtex™-E 1.8 V Field Programmable Gate Arrays
0.05
0.05
Min
0.0
Speed Grade
0.9 / 0
0.9 / 0
2.0 / 0
1.8 / 0
1.7 / 0
2.46
1.2
1.2
2.4
0.092
0.092
T
-8
Symbol
T
Speed Grade
T
0.0
TCKTDO
TCKTAP
-8
F
TAPTK
TCK
1.0 / 0
1.0 / 0
2.2 / 0
2.1 / 0
2.0 / 0
1.35
1.35
0.10
0.10
3.1
2.7
-7
0.0
(1)
-7
Value
11.0
4.0
2.0
33
1.1 / 0
1.1 / 0
2.5 / 0
2.3 / 0
2.2 / 0
0.11
0.11
0 .0
3.5
1.5
1.5
3.0
-6
-6
MHz, max
Module 3 of 4
ns, max
ns, min
ns, min
ns, max
ns, max
ns, max
Units
ns, max
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
Units
Units
17

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