MAX3543CTL+ Maxim Integrated Products, MAX3543CTL+ Datasheet - Page 8

• Manufacturer Part Number: MAX3543CTL+
• Description: RF Receiver Multi-band Ananlog a and Digital TV Tuner
• Manufacturer: Maxim Integrated Products

Specifications of MAX3543CTL+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Multiband Analog and
Digital Television Tuner
*Improper placement of these inductors degrades image rejection, gain, and noise figure. Copy Maxim reference design layout
exactly in this area.
The MAX3543 uses a 2-wire I
face consisting of a serial data line (SDA) and a serial
clock line (SCL). SDA and SCL facilitate bidirectional
communication between the MAX3543 and the master
at clock frequencies up to 400kHz. The master initiates a
data transfer on the bus and generates the SCL signal to
permit data transfer. The MAX3543 behaves as a slave
device that transfers and receives data to and from the
master. Pull SDA and SCL high with external pullup resis-
tors for proper bus operation.
One bit is transferred during each SCL clock cycle. A
minimum of nine clock cycles is required to transfer a
byte in or out of the MAX3543 (8 data bits and an ACK/
NACK). The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while SCL is high and stable are considered control sig-
nals (see the START and STOP Conditions section). Both
SDA and SCL remain high when the bus is not busy.
The master initiates a transmission with a START condi-
tion (S), which is a high-to-low transition on SDA while
SCL is high. The master terminates a transmission with a
STOP condition (P), which is a low-to-high transition on
SDA while SCL is high.
8
______________________________________________________________________________________
PIN
30
31
32
33
34
35
36
37
38
40
—
EP (GND) Exposed Paddle Ground. Solder evenly to the PCB ground plane for proper operation.
TFU2A*
TFU2B*
TFVH1*
TFVH2*
TFVL1*
TFVL2*
NAME
TFU1*
TFU3*
RFINL
LEXT*
I
2
C-Compatible Serial Interface
Detailed Description
VHF Low Tracking Filter 1
VHF Low Tracking Filter 2
VHF High Tracking Filter 1
VHF High Tracking Filter 2
UHF Tracking Filter 1
UHF Tracking Filter 2A
UHF Tracking Filter 2B
UHF Tracking Filter 3
RF VGA Supply Voltage. Connect through a 270nH pullup inductor to V
Low-Frequency RF Input. Matched to 75I over the operating band. Requires a DC-blocking capacitor.
START and STOP Conditions
2
C-compatible serial inter-
Table 2. Address Configurations
Data transfers are framed with an acknowledge bit (ACK)
or a not-acknowledge bit (NACK). Both the master and
the MAX3543 (slave) generate acknowledge bits. To
generate an acknowledge, the receiving device must
pull SDA low before the rising edge of the acknowledge-
related clock pulse (ninth pulse) and keep it low during
the high period of the clock pulse.
To generate a not-acknowledge condition, the receiver
allows SDA to be pulled high before the rising edge
of the acknowledge-related clock pulse, and leaves
SDA high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data trans-
fer happens if a receiving device is busy or if a system
fault has occurred. In the event of an unsuccessful data
transfer, the bus master must reattempt communication
at a later time.
The MAX3543 has a 7-bit slave address plus one R/W
bit. These 8 bits must be sent to the device following a
START condition to initiate communication. The slave
address is determined by the state of the ADDR pin as
shown in Table 2.
Unconnected
ADDR PIN
FUNCTION
Acknowledge and Not-Acknowledge Conditions
0
1
Pin Description (continued)
ADDR2
0
0
1
ADDR1
CC
0
1
0
.
ADDRESS
WRITE
0xC0
0xC2
0xC4
Slave Address
ADDRESS
READ
0xC1
0xC3
0xC5