MAX2390ETI+T Maxim Integrated Products, MAX2390ETI+T Datasheet - Page 27

• Manufacturer Part Number: MAX2390ETI+T
• Description: RF Receiver IC RECEIVERS ZERO-IF-EP
• Manufacturer: Maxim Integrated Products

Specifications of MAX2390ETI+T

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

With the exception of the analog-input AGC, all func-
tionality of these direct-conversion receivers can be
controlled through the 3-wire serial interface
(SPI™/QSPI™/MICROWIRE™ compatible).
All devices in this family have two programmable 20-bit
registers: the configuration register (CONFIG) and the
control register (OPCNTRL). The MAX2391/MAX2392/
MAX2393/MAX2401 have two additional programmable
20-bit registers: the main PLL divide register (RFM) and
the reference PLL divide register (RFR). The 4 least sig-
nificant bits of the data sent are the register’s address.
The 16 most significant bits are used for register data.
All registers contain a few don’t care bits. These can be
either 0 or 1 and do not affect operation.
1b provide a register summary. Data is shifted in MSB
first. When CS is low, data is shifted with the rising
edge of the clock. When CS transitions to high, the shift
register is latched into the register selected by the con-
tents of the address bits. Power-up defaults for the four
registers are shown in
The RFM register sets the main-frequency divide ratio
for the RF PLL. The RFR register sets the reference-fre-
quency divide ratio. The RF LO frequency can be
determined by the following:
where f
MICROWIRE is a trademark of National Semiconductor Corp.
SPI and QSPI are trademarks of Motorola, Inc.
Table
REGISTER
OPCNTRL
CONFIG
NAME
RFM
RFR
W-CDMA/W-TDD/TD-SCDMA Zero-IF Receivers
RF LO frequency = f
REFIN
1a. Register Defintion (MAX2390–MAX2393, MAX2401)
MSB
B15 B14 B13 B12 B11 B10
is the external input reference frequency
______________________________________________________________________________________
Detailed Description
Table
REFIN
2.
Register Definition
x (RFM / RFR)
Tables
B9
20-BIT REGISTER
DATA 16 BITS
1a and
B8
B7
B6
for the MAX2390–MAX2393, MAX2401.
The operation control register (OPCNTRL) and the con-
figuration register (CONFIG) are used to program the
receiver for the appropriate mode of operation. See
Tables 3 and 4 for the function of each bit.
The test register is used to set the receiver in factory
testing mode. It should only be programmed at receiver
turn-on with the word 0370 (hex) for MAX2390–MAX2393,
MAX2401 and 2370 (hex) for MAX2396/MAX2400.
Bias control is distributed among several functional sec-
tions and can be controlled to accommodate different
power-down modes as shown in
The IC has three bias states: SHUTDOWN, IDLE, and
ON. SHUTDOWN can be asserted by either a hardware
control line (SHDN) or by bit 5 of the operation control
register (OPCTRL.SHDN). When the serial interface is
used to shut down the part, an internal linear regulator,
with IQ ≈ 90µA, stays functional to keep the serial inter-
face operational. Use the SHDN logic-control pin to
bring quiescent current below 10µA. Register bit set-
tings maintain their values after a hard shutdown, pro-
vided CS remains high. IDLE mode disables the LNA,
I/Q mixers, and baseband circuitry, but keeps the serial
interface and synthesizer operational, dropping quies-
cent current to 11.5mA. The entire receiver is ON when
SHDN
OPCNTRL.IDLE bits (MAX2390–MAX2393, MAX2401)
or the IDLE pin (MAX2396/MAX2400) are set to 1; the
typical supply current is 32mA.
B5
is
B4
high
B3
B2
and
B1
OPCNTRL.SHDN
Power Management
B0
Table
A3
0
0
1
1
ADDRESS 4 BITS
5.
A2
0
1
0
1
A1
1
1
1
1
LSB
and
A0
1
1
1
1
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