MAX2390ETI+T Maxim Integrated Products, MAX2390ETI+T Datasheet - Page 32

• Manufacturer Part Number: MAX2390ETI+T
• Description: RF Receiver IC RECEIVERS ZERO-IF-EP
• Manufacturer: Maxim Integrated Products

Specifications of MAX2390ETI+T

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The LNA requires a simple two-element 50Ω matching
network at the input. Use the layout and matching net-
work provided in the EV kit as a reference. The LNA input
is internally biased, so be sure to use a series 100pF DC
blocking capacitor in front of the matching network.
The LNA offers a 23dB gain step with less than 10
degrees phase change, selectable with either a dedi-
cated logic pin (G_LNA) or bit 3 in the operation control
register (OPCTRL.GLNA).
LNA output matching is provided on-chip, offering bet-
ter than 2:1 VSWR. The required DC blocking capacitor
is provided on-chip, so the LNA output can be connect-
ed directly to the RF SAW filter or balun.
The mixers’ differential input impedance is 200Ω, allow-
ing an easy interface to commercially available differ-
ential-output Rx SAW filters or 1:4 baluns. No DC
blocks are required, but a single, small shunt inductor
is required to resonate out the parasitic capacitance
from the SAW filter and IC package.
The mixer offers an 11dB gain step, which is controlled
by either the logic-control pin (G_MXR) or bit 1 of the
operation control register (OPCTRL.GMXR). This offers
the option to switch the mixer into a low-gain state if
required, reducing current consumption by about 3mA.
Use the mixer gain step and AGC before reducing LNA
gain for optimum receiver dynamic range.
All receiver channel selectivity is implemented fully on-
chip, with greater than 40dB adjacent channel selectivi-
ty (ACS). This eliminates the need for any additional
filtering by any subsequent baseband processor.
The group delay of the integrated filters is compensat-
ed through on-chip equalizers for optimum EVM.
The AGC circuitry of the baseband amplifiers offers lin-
ear (dB/V) gain control for the receiver. With the AGC
voltage from 0.3V to 2.4V, the VGA section provides
60dB gain-control range, for a total of 95dB including
the LNA and mixer gain steps.
The AGC control line has an input impedance of more
than 100kΩ at DC. Internal capacitance creates a single
W-CDMA/W-TDD/TD-SCDMA Zero-IF Receivers
32
______________________________________________________________________________________
Applications Information
LNA and RFIN Matching
Baseband I/Q Filters
I/Q Mixers
AGC
pole at approximately 2MHz; this provides some high-
frequency filtering, thereby reducing AM distortion.
For applications using a baseband processor with digi-
tal-only AGC, Maxim offers an 8-bit voltage-output AGC
DAC with an SPI/QSPI/MICROWIRE interface in a tiny
6-pin SOT23 package. Especially designed as a low-
cost, all-in-one solution for cellular handset AGC, the
MAX5383 offers the following features: a serial interface
good to 10MHz, guaranteed operation from a 2.7V to
3.6V supply, on-chip 2V reference, <±10% full-scale
error, <±1LSB INL/DNL, <1µA shutdown, and a minis-
cule 150µA supply current. See the Typical Application
Circuits for example application circuits using an exter-
nal AGC DAC.
For optimum IP2 and lowest DC offset at the baseband
outputs, a 3-pole Butterworth highpass filter is imple-
mented on-chip. In normal operation, this highpass cor-
ner is set to 8.6kHz. The corner frequency is chosen to
optimize DC settling time when the system is faced with
large DC transients due to an LNA gain step or a large
AGC change between receive bursts.
An additional adaptive DC-cancellation mode has been
implemented, which is activated for any of the following
events: IC is enabled with IDLE, IC is enabled with
SHDN, an LNA gain step (through logic pin or register
setting), or a mixer gain step (through logic pin or reg-
ister setting). This adaptive DC correction loop further
minimizes DC settling time for cases where large DC
errors are introduced. For further flexibility, the SPI
interface can be used to sequence the DC cancellation
loop through different time constants (see
The baseband I and Q differential outputs are designed
for a 150mV
The 8dB peak-to-average ratio of the forward W-CDMA
channel brings the typical voltage at the baseband out-
puts to 1.0V
DC-coupled, and offer a programmable common-mode
voltage to address the requirements of different base-
band processors’ ADCs. The output common-mode volt-
age is 1.2V with OPCTRL VCM = 0, and 1.4V for VCM = 1
(see
These outputs are designed for a minimum load of
10kΩ (differential) in parallel with 5pF.
Table
2 for the OPCTRL register definitions).
RMS
P-P
. The baseband amplifiers’ outputs are
W-CDMA combined signal plus noise.
Baseband I/Q Interface
DC Offset Correction
Table
3).