DLP-HS-FPGA2 DLP Design Inc, DLP-HS-FPGA2 Datasheet - Page 4

• Manufacturer Part Number: DLP-HS-FPGA2
• Description: Interface Modules & Development Tools USB FPGA Module w/ Xilinx XC3S400A
• Manufacturer: DLP Design Inc
• Series: -r

Specifications of DLP-HS-FPGA2

• Interface Type: USB
• Description/function: USB - FPGA Module
• Dimensions: 71.1 mm x 30.5 mm x 5.3 mm
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Number Of Channels: 2
• Operating Supply Voltage: 3.6 V to 6 V
• Product: Interface Modules
• Supply Voltage (max): 6 V
• Supply Voltage (min): 3.6 V
• Wireless Frequency: 66 MHz
• Main Purpose: Interface, USB to FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: FT2232D, XC3S400A-4FTG256C
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Xilinx Spartan 3A, FTDI FT2232H Dual-Channel High-Speed USB IC

The User I/O Block controls access to the 63 user I/O pins accessible through the top- and bottom-
side headers. Every one of these pins can be either an input or an output. The User I/O Block can
configure these pins as inputs and read their state, or as outputs and drive them high or low. (As a
side note, 48 of these user I/O pins can be configured as 24 differential pairs, 8 can be configured as
global clock inputs and 6 can be configured as regional clock inputs.)
The DDR2 SDRAM interface block manages the memory’s initialization, the refresh cycle and the
read and write access. Read and write access is available in 4-byte bursts. The traces between the
DDR2 SDRAM and FPGA are matched within 10 mils to accommodate reliable data transfer at 266
Mbit/s (clocked at 133MHz). The interface creates and aligns the Data Strobes (DQS) based on an
external feedback trace that matches two times the trace length between the FPGA and the DDR2
SDRAM. The Initialization, Read and Write commands are initiated by the USB interface block and
executed by the DDR2 SDRAM interface block.
The Heartbeat Pulse Generator takes the internal system clock and divides it down so that the
onboard Heartbeat LED will be turned on and off for a duration of approximately one-half second.
The Clock Generator Block receives the 66-MHz clock and produces both the 133-MHz clocks
required to run the DDR2 SDRAM memory device and the 100-MHz clock for the remaining internal
logic in the FPGA. It also handles reset and lock synchronization between internal DCM blocks.
The design occupies the following FPGA resources on the DLP-HS-FPGA module’s XC3S200A:
The design occupies the following FPGA resources on the DLP-HS-FPGA2 module’s XC3S400A:
Rev. 1.3 (March 2011)
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© DLP Design, Inc.