DLP-HS-FPGA2 DLP Design Inc, DLP-HS-FPGA2 Datasheet - Page 7

• Manufacturer Part Number: DLP-HS-FPGA2
• Description: Interface Modules & Development Tools USB FPGA Module w/ Xilinx XC3S400A
• Manufacturer: DLP Design Inc
• Series: -r

Specifications of DLP-HS-FPGA2

• Interface Type: USB
• Description/function: USB - FPGA Module
• Dimensions: 71.1 mm x 30.5 mm x 5.3 mm
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Number Of Channels: 2
• Operating Supply Voltage: 3.6 V to 6 V
• Product: Interface Modules
• Supply Voltage (max): 6 V
• Supply Voltage (min): 3.6 V
• Wireless Frequency: 66 MHz
• Main Purpose: Interface, USB to FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: FT2232D, XC3S400A-4FTG256C
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: Xilinx Spartan 3A, FTDI FT2232H Dual-Channel High-Speed USB IC

7.0 JTAG INTERFACE
The easiest way to load an FPGA configuration (*.bit) file to the FPGA is to run the BitLoadApp
software then select and program a file from the local hard drive directly to the SPI Flash. Once
written to the SPI Flash, the configuration will load to the FPGA and execute. Alternatively, a
traditional JTAG header location is provided on the DLP-HS-FPGA giving the user access to the
specific pins required by the development tools. (Refer to the schematic contained within this
datasheet for details.)
8.0 EEPROM SETUP / MPROG
The DLP-HS-FPGA has a dual-channel USB interface to the host PC. Channel A is used exclusively
to load an FPGA configuration (*.bit) file to the SPI Flash. This configuration data is automatically
transferred to the FPGA when power is applied to the module or when the PROG Pin is driven low
and then released by the application software. Channel B is used for communication between the
FPGA and host PC at run time. A 93LC56B EEPROM connected to the USB interface IC is used to
store the setup for the two channels. The parameters stored in the EEPROM include the Vendor ID
(VID), Product ID (PID), Serial Number, Description String, driver selection (VCP or D2XX) and port
type (UART serial or FIFO parallel).
As mentioned above, Channel A is used exclusively for loading the FPGA’s configuration to the SPI
Flash, and Channel B is used for communication between the host PC and the DLP-HS-FPGA. As
such, the D2XX drivers and 245 FIFO mode must be selected in the EEPROM for Channel A.
Channel B must use the 245 FIFO mode, but it can use either the VCP or D2XX drivers. The VCP
drivers make the DLP-HS-FPGA appear as an RS232 port to the host application. The D2XX drivers
provide faster throughput, but require working with a *.lib or *.dll library in the host application.
The operational modes and other EEPROM selections are written to the EEPROM using the MPROG
utility. This utility and its manual are available for download from the bottom of the page at
www.dlpdesign.com.
Rev. 1.3 (March 2011)
7
© DLP Design, Inc.