EVAL-ADUC834QS Analog Devices Inc, EVAL-ADUC834QS Datasheet - Page 62

• Manufacturer Part Number: EVAL-ADUC834QS
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADUC834QS

• Lead Free Status / RoHS Status: Not Compliant

ADuC834
Interrupt Priority
The Interrupt Enable registers are written by the user to enable
individual interrupt sources, while the Interrupt Priority registers
allow the user to select one of two priority levels for each inter-
rupt. An interrupt of a high priority may interrupt the service
routine of a low priority interrupt, and if two interrupts of different
priority occur at the same time, the higher level interrupt will be
serviced first. An interrupt cannot be interrupted by another
interrupt of the same priority level. If two interrupts of the same
priority level occur simultaneously, a polling sequence is used to
determine which interrupt is serviced first. The polling sequence
is shown in Table XXXVIII.
Source
PSMI
WDS
IE0
RDY0/RDY1
TF0
IE1
TF1
ISPI/I2CI
RI + TI
TF2 + EXF2
TII
Table XXXVIII. Priority within an Interrupt Level
Priority
1 (Highest)
2
3
4
5
6
7
8
9
10
11 (Lowest)
Description
Power Supply Monitor Interrupt
Watchdog Interrupt
External Interrupt 0
ADC Interrupt
Timer/Counter 0 Interrupt
External Interrupt 1
Timer/Counter 1 Interrupt
SPI Interrupt
Serial Interrupt
Timer/Counter 2 Interrupt
Time Interval Counter Interrupt
–62–
Interrupt Vectors
When an interrupt occurs, the program counter is pushed onto
the stack and the corresponding interrupt vector address is
loaded into the program counter. The interrupt vector addresses
are shown in Table XXXIX.
Source
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
RDY0/RDY1 (ADC)
ISPI/I2CI
PSMI
TII
WDS (WDIR = 1)*
*The watchdog can be configured to generate an interrupt instead of a reset
when it times out. This is used for logging errors or to examine the internal
status of the microcontroller core to understand, from a software debug point
of view, why a watchdog timeout occurred. The watchdog interrupt is slightly
different from the normal interrupts in that its priority level is always set to 1
and it is not possible to disable the interrupt via the global disable bit ( EA) in
the IE SFR. This is done to ensure that the interrupt will always be responded
to if a watchdog timeout occurs. The watchdog will only produce an interrupt
if the watchdog timeout is greater than zero.
Table XXXIX. Interrupt Vector Addresses
0003H
000BH
0013H
001BH
0023H
002BH
0033H
003BH
0043H
0053H
005BH
Vector Address
REV. A