EVAL-ADUC834QS Analog Devices Inc, EVAL-ADUC834QS Datasheet - Page 79

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EVAL-ADUC834QS

Manufacturer Part Number
EVAL-ADUC834QS
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of EVAL-ADUC834QS

Lead Free Status / RoHS Status
Not Compliant
Parameter
I
*Input filtering on both the SCLOCK and SDATA inputs surpresses noise spikes less than 50 ns.
REV. A
2
C-SERIAL INTERFACE TIMING
t
t
t
t
t
t
t
t
t
t
t
L
H
SHD
DSU
DHD
RSU
PSU
BUF
R
F
SUP*
SDATA (I/O)
SCLK (I)
SCLOCK Low Pulsewidth
SCLOCK High Pulsewidth
Start Condition Hold Time
Data Setup Time
Data Hold Time
Setup Time for Repeated Start
Stop Condition Setup Time
Bus Free Time between a STOP
Condition and a START Condition
Rise Time of Both SCLOCK and SDATA
Fall Time of Both SCLOCK and SDATA
Pulsewidth of Spike Suppressed
t
PSU
CONDITION
STOP
PS
t
BUF
CONDITION
START
t
DSU
t
SHD
Figure 79. I
MSB
1
t
DHD
2
C Compatible Interface Timing
2-7
–79–
t
L
LSB
8
4.7
4.0
0.6
0.6
0.6
1.3
Min
100
t
SUP
t
H
t
DSU
t
SUP
ACK
9
Max
0.9
300
300
50
t
RSU
t
DHD
REPEATED
START
S(R)
Unit
µs
µs
µs
ns
µs
µs
µs
µs
ns
ns
ns
t
F
MSB
t
F
1
t
R
t
R
ADuC834
Figure
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