EVAL-ADUC834QS Analog Devices Inc, EVAL-ADUC834QS Datasheet - Page 78

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EVAL-ADUC834QS

Manufacturer Part Number
EVAL-ADUC834QS
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of EVAL-ADUC834QS

Lead Free Status / RoHS Status
Not Compliant
ADuC834
Parameter
SPI SLAVE MODE TIMING (CPHA = 0)
t
t
t
t
t
t
t
t
t
t
t
t
t
SS
SL
SH
DAV
DSU
DHD
DF
DR
SR
SF
SSR
DOSS
SFS
SS to SCLOCK Edge
SCLOCK Low Pulsewidth
SCLOCK High Pulsewidth
Data Output Valid after SCLOCK Edge
Data Input Setup Time before SCLOCK Edge
Data Input Hold Time after SCLOCK Edge
Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
SS to SCLOCK Edge
Data Output Valid after SS Edge
SS High after SCLOCK Edge
(CPOL = 0)
(CPOL = 1)
SCLOCK
SCLOCK
MISO
MOSI
SS
t
DOSS
t
SS
t
DSU
MSB IN
Figure 78. SPI Slave Mode Timing (CPHA = 0)
MSB
t
DHD
t
SH
t
DF
t
DAV
t
SL
t
DR
BITS 6–1
BITS 6–1
–78–
Min
0
100
100
0
Typ
330
330
10
10
10
10
LSB IN
t
SR
LSB
Max
50
25
25
25
25
50
20
t
SF
t
SFS
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure
78
78
78
78
78
78
78
78
78
78
78
78
78
REV. A