EVAL-ADUC834QS Analog Devices Inc, EVAL-ADUC834QS Datasheet - Page 76

• Manufacturer Part Number: EVAL-ADUC834QS
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADUC834QS

• Lead Free Status / RoHS Status: Not Compliant

ADuC834
Parameter
SPI MASTER MODE TIMING (CPHA = 0)
*Characterized under the following conditions:
a. Core clock divider bits CD2, CD1 and CD0 in PLLCON SFR set to 0, 1, and 1 respectively, i.e., core clock frequency = 1.57 MHz, and
b. SPI bit-rate selection bits SPR1 and SPR0 in SPICON SFR set to 0 and 0 respectively.
t
t
t
t
t
t
t
t
t
t
SL
SH
DAV
DOSU
DSU
DHD
DF
DR
SR
SF
SCLOCK Low Pulsewidth*
SCLOCK High Pulsewidth*
Data Output Valid after SCLOCK Edge
Data Output Setup before SCLOCK Edge
Data Input Setup Time before SCLOCK Edge
Data Input Hold Time after SCLOCK Edge
Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
(CPOL = 0)
(CPOL = 1)
SCLOCK
SCLOCK
MOSI
MISO
Figure 76. SPI Master Mode Timing (CPHA = 0)
t
DAV
t
SH
t
DSU
MSB IN
t
DHD
MSB
t
SL
t
DF
–76–
Min
100
100
t
DR
BITS 6–1
BITS 6–1
Typ
630
630
10
10
10
10
t
SR
Max
50
150
25
25
25
25
LSB IN
t
SF
LSB
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure
76
76
76
76
76
76
76
76
76
76
REV. A