MT48LC4M32B2B5-7 IT:G Micron Technology Inc, MT48LC4M32B2B5-7 IT:G Datasheet - Page 10
![DRAM Chip SDRAM 128M-Bit 4Mx32 3.3V 90-Pin VFBGA Tray](/photos/7/23/72313/mfg557-90-vfbga_sml.jpg)
MT48LC4M32B2B5-7 IT:G
Manufacturer Part Number
MT48LC4M32B2B5-7 IT:G
Description
DRAM Chip SDRAM 128M-Bit 4Mx32 3.3V 90-Pin VFBGA Tray
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC4M32B2P-7G_TR.pdf
(67 pages)
Specifications of MT48LC4M32B2B5-7 IT:G
Density
128 Mb
Maximum Clock Rate
143 MHz
Package
90VFBGA
Address Bus Width
14 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
17|8|5.5 ns
Operating Temperature
-40 to 85 °C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
128M (4Mx32)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
90-VFBGA
Organization
4Mx32
Address Bus
14b
Access Time (max)
17/8/5.5ns
Operating Supply Voltage (typ)
3.3V
Package Type
VFBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
175mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 5:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. L 1/09 EN
A8, A2, C3, A1, C2,
G2, G3, H1, H2, J3,
D8, B9, C8, A9, C7,
G8, G9, F7, F3, G1,
R8, N7, R9, N8, P9,
R1, N3, R2, E8, D7,
E3, E7, H3, H7, K2,
B2, B7, C9, D9, E1,
B8, B3, C1, D1, E9,
L1, M9, N9, P2, P7
L9, M1, N1, P3, P8
90-Ball VFBGA
M3, M2, P1, N2,
M8, M7, L8, L2,
B1, D2, D3, E2
K9, K1, F8, F2
A7, F9, L7, R7
A3, F1, L3, R3
J9, K7, K8
G7, H9
J7, H8
K3
J1
J2
J8
Ball Descriptions
BA0, BA1
DQM0–3
Symbol
A0–A11
RAS#,
CAS#,
DQ31
V
DQ0–
V
WE#
CKE
V
CLK
CS#
V
NC
DD
SS
DD
SS
Q
Q
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Type
I/O
–
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled
on the positive edge of CLK. CLK also increments the internal burst counter
and controls the output registers.
Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides precharge power-down and SELF REFRESH
operation (all banks idle), active power-down (row active in any bank) or
CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous
except after the device enters power-down and self refresh modes, where CKE
becomes asynchronous until after exiting the same mode. The input buffers,
including CLK, are disabled during power-down and self refresh modes,
providing low standby power. CKE may be tied HIGH.
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH, but
READ/WRITE bursts already in progress will continue and DQM operation will
retain its DQ mask capability while CS# is HIGH. CS# provides for external bank
selection on systems with multiple banks. CS# is considered part of the
command code.
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command
being entered.
Input/Output mask: DQM is sampled HIGH and is an input mask signal for write
accesses and an output enable signal for read accesses. Input data is masked
during a WRITE cycle. The output buffers are placed in a High-Z state (two-
clock latency) when during a READ cycle. DQM0 corresponds to DQ0–DQ7,
DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–DQ23 and
DQM3 corresponds to DQ24–DQ31. DQM0–3 are considered same state when
referenced as DQM.
Bank address input(s): BA0 and BA1 define to which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied. These pins also provide the
op-code during a LOAD MODE REGISTER command.
Address inputs: A0–A11 are sampled during the ACTIVE command (row-
address A0–A11) and READ/WRITE command (column-address A0–A7; with A10
defining auto precharge) to select one location out of the memory array in the
respective bank. A10 is sampled during a PRECHARGE command to determine
if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1
(LOW). The address inputs also provide the op-code during a LOAD MODE
REGISTER command.
Data input/output: Data bus
No connect: These pins should be left unconnected. H7 is a not connect for this
part but may be used as A12 in future designs.
DQ power: Provide isolated power to DQs for improved noise immunity.
DQ ground: Provide isolated ground to DQs for improved noise immunity.
Power supply: Voltage dependant on option.
Ground.
10
Pin/Ball Assignments and Descriptions
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Description
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM