MT48LC4M32B2B5-7 IT:G Micron Technology Inc, MT48LC4M32B2B5-7 IT:G Datasheet - Page 55
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MT48LC4M32B2B5-7 IT:G
Manufacturer Part Number
MT48LC4M32B2B5-7 IT:G
Description
DRAM Chip SDRAM 128M-Bit 4Mx32 3.3V 90-Pin VFBGA Tray
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC4M32B2P-7G_TR.pdf
(67 pages)
Specifications of MT48LC4M32B2B5-7 IT:G
Density
128 Mb
Maximum Clock Rate
143 MHz
Package
90VFBGA
Address Bus Width
14 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
17|8|5.5 ns
Operating Temperature
-40 to 85 °C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
128M (4Mx32)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
90-VFBGA
Organization
4Mx32
Address Bus
14b
Access Time (max)
17/8/5.5ns
Operating Supply Voltage (typ)
3.3V
Package Type
VFBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
175mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 38:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. L 1/09 EN
Single READ – Without Auto Precharge
DQML, DQMH
COMMAND
A0–A9, A11
BA0, BA1
Notes:
DQM /
CKE
CLK
A10
DQ
t CMS
t CKS
t AS
t AS
t AS
1. For this example, BL = 4, CL = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. x16: A9 and A11 = “Don’t Care”
ACTIVE
T0
ROW
ROW
BANK
x32: A8, A9,and A11 = “Don’t Care”
See Table 18 on page 46.
t CKH
t CMH
t AH
t AH
t AH
t RCD
t RAS
t RC
t CK
T1
NOP
DISABLE AUTO PRECHARGE
t CMS
t CL
COLUMN m 2
T2
BANK
READ
t CH
t CMH
CAS Latency
55
SINGLE BANK
PRECHARGE
ALL BANKS
BANK
T3
t LZ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t RP
t AC
T4
NOP
D
OUT
t OH
t HZ
m
ROW
BANK
ROW
T5
ACTIVE
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
DON’T CARE
UNDEFINED
Timing Diagrams